Invited paperA brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
Introduction
Electrically active gate oxide defects are an inevitable reality of MOS-based devices. Indeed, their control and reduction in silicon dioxide was one of the main enablers of silicon-based microelectronics [1], [2]. The excess of gate oxide defects is also the main roadblock for post-Si MOS technologies, such as those based on Ge and IIIV channels [3]. Gate oxide defects are responsible for sub-optimal FET parameters of as-fabricated devices, such as mobility, sub-threshold slope, and threshold voltage, as well as a further degradation of these parameters during device operation. Depending on the type of measurement and the measurement conditions, these time-dependent instabilities are commonly referred to as hysteresis, Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), the latter observable in smaller-area devices.
Negative BTI (NBTI), observed since the early period of MOSFET technology, remains a critical issue in present-day Si-based p-channel MOSFETs [4], [5]. With the introduction of high-k gate dielectrics, Positive BTI (PBTI) emerged as a concern for n-channel MOSFETs, later on minimized by high-k material quality improvement; nevertheless, PBTI still represents a concern for beyond-Si technologies [3], [6].
In general, the instabilities are caused by charging and discharging of as-fabricated and generated bulk and interface states [7], [8], [9]. Over the last decade we have concluded that a large body of observations in a range of Si and post-Si gate stacks can be explained if the detailed properties of the gate oxide defects are understood and invoked. Primarily, the trap energy levels in the gate dielectric and their misalignment with the channel Fermi level offer a picture that can explain many features of both PBTI and NBTI in a range of stacks. The channel/trap energy level misalignment is also proposed as the most efficient method to reduce BTI, particularly in post-Si gate stacks, and is discussed in the next section, i.e., Section 2.
The rapid downscaling of FET devices brought about the possibility to observe individual trapping and detrapping events and with it, direct experimental access to additional trap properties. These include the internal barriers associated with the trap atomic reconfiguration (aka structural relaxation) during carrier capture and emission, which are e.g. responsible for the strong temperature dependence of the capture and emission times. A closer investigation then revealed even a more intricate, multi-state structure of some traps, allowing to explain complex RTN behavior, such as anomalous RTN and capture time frequency dependence [10], [11].
Apart from their temporal properties, the electrostatics of single traps could be investigated in deeply scaled devices. The effect of single traps on the FET characteristics depends on the trap depth in the oxide, lateral position above the channel, as well as random variations in the FET channel potential [12]. The main properties of individual defects are reviewed in Section 3.
Decomposing transistor gate oxide reliability down into individual traps and their well understood properties allows us to reassess and reassemble the time-dependent behavior of deeply scaled devices from “bottom up” [13]. The collective action of several traps in each device results in within-device and device-to-device time-dependent variability [9]. The methods of incorporating this variability in reliability-aware circuit simulations, the practical application of our understanding, are briefly mentioned in Section 4.
Section snippets
Trap level perspective of BTI
Positive BTI (PBTI) came into prominence with the advent of high-k gate oxides [14]. We and others have noticed that the inclusion of rare earth elements in the high-k layer results in the reduction of the threshold voltage shift ΔVth after a PBTI stress, Fig. 1 [15], [16]. Remarkably, the instability reduction is accompanied by a larger oxide electric field (or gate voltage) dependence. A larger field (or voltage) power-law exponent γ (i.e., the slope in a log-log plot) for the stack with
Oxide trap properties
When the stress bias is removed from the FET gate, BTI degradation starts to recover immediately. Especially ΔVth recovery (aka relaxation) is archetypal for the BTI measurement. It has been the source of most of the controversy surrounding the BTI phenomenon, also because it complicates comparison of results if not duly measured and specified.
The ΔVth relaxation in large devices is log-like and typically featureless, Fig. 6a [30]. It is observed to already be in progress at 1 μs or less after
Implications for devices and circuits
In the previous section we have seen that each trap behaves stochastically around mean values that vary widely from trap to trap. In large-area devices the individual behavior of the many traps averages out and noise measurements are the only way to access the trap stochastic properties. As a consequence, large-area devices all degrade approximately identically in standard BTI experiments and the lifetime can be defined as a single value, determined by a parameter, e.g. ΔVth, crossing a
Conclusions
We have reviewed a BTI paradigm based on gate oxide traps and the detailed understanding of their properties. The trap energy levels in the gate dielectric and their misalignment with the channel Fermi level offers the most effective strategy to reduce both PBTI and NBTI in a range of stacks. The trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as internal thermal barriers of the trap, related to atomic reconfiguration. The
Acknowledgements
The presented work has been performed within the imec Logic INSITE Partner Program. The work has been in part supported by the European Commission under FP7 project 261868 (MORDRED) and project 619234 (MoRV).
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