Elsevier

Microelectronics Reliability

Volume 82, March 2018, Pages 190-196
Microelectronics Reliability

Study and analysis of DR-VCO for rad-hardness in type II third order CPLL

https://doi.org/10.1016/j.microrel.2018.01.018Get rights and content

Highlights

  • •

    It reports on radiation hardness of differential ring (DR-VCO) designed using 90 nm CMOS process in Type II third order CPLL for different number of delay cell stages running at 2.6 GHz frequency.

  • •

    The influence of number of delay cells used in DR-VCO in Type II third order CPLL for reducing phase displacement caused by Single Event Transient (SET) has been analyzed using small signal model and feedback theory. The simulation has been done for varying LET values from 20 to 200 MeV-cm2/mg.

  • •

    simulation result shows that the erroneous cycles produced by CPLL with 11 stage VCO in response to SET hit with LET value of 200 MeV-cm2/mg achieves 53% improvement compare to CPLL with 3 stage VCO.

Abstract

In this paper, suitability of differential ring VCO designed using 90 nm CMOS process for the SET environment is studied for number of delay stages ranging from three to eleven operating at 2.6 GHz frequency. Effect of increasing the number of VCO delay cell stages to suppress SET strike sensitivity of oscillator has been studied for Linear Energy Transfer (LET) values between 20 and 200 MeV-cm2/mg. To further validate the relation between the number of stages used in VCO architecture and SET tolerance level, the differential ring VCOs are tested within a type II 3rd order CPLL operating at the same frequency. Circuit simulations show that the PLL performance parameters: settling behaviour and error cycles of PLL are strongly correlated to the number of delay stages used in the VCO. The error cycles produced by CPLL with 11 stage VCO in response to SET hit with LET value of 200 MeV-cm2/mg achieves 53% improvement compared to CPLL with 3 stage VCO.

Introduction

The performance of nanoscale CMOS circuits has improved significantly with technology scaling. However, with shrinking feature size, supply voltage and node capacitances have scaled down as well [1,2]. Reliability of electronic circuits designed to work in radiation environments such as nuclear facilities, avionics, defence and space applications has become a major concern for electronic circuit designers as the logic state of a node could be easily flipped when energetic heavy ions such as protons, neutrons or alpha particles hit the source/drain diffusion of MOSFETs. The heavy ion strikes will result in Single Event Upsets (SEU) in memory and logic circuits [[3], [4], [5], [6]]. On the other hand, in analog circuits, these ionizing particles could produce Single Event Transients (SETs) in MOSFETs which will result in non-destructive effect such as transient variation in output voltage.

Phase Locked Loops (PLLs) are broadly used in mixed-signal integrated-circuits for numerous applications such as clock generation and recovery, frequency multiplication and local oscillator signal generation for mixer blocks in transceivers [[7], [8], [9]]. In a high-speed digital communication system, the performance of PLL is crucial for reduced bit error rate. PLL resilience is essential to reduce the vulnerability of PLL so as to reduce bit errors in clocked circuits under radiation environment. Recent researches have focused on characterizing SETs in PLL blocks for radiation hardened design. Among the functional blocks of PLL such as Phase Frequency Detector (PFD), Low Pass Filter (LP) Charge Pump (CP), and Voltage Controlled Oscillator (VCO); the CP and VCO have been identified as the most vulnerable to SETs [[10], [11], [12], [13], [14]]. To improve SET tolerance in PLL, tristate voltage based charge pump and current based charge pump using current compensation technique have been proposed in [10,11]. Radiation hardening for current starved VCO based PLL has been proposed in [[12], [13], [14]]. In [15] Triple Modular Redundancy (TMR) technique, majority voter circuit has been used to reduce radiation-induced jitter. Since VCO dominates the single Event (SE) susceptibility of PLL [13]; phase displacement study for LC-VCOs and different ring oscillator topologies (single ended current starved inverter based and differential ring oscillator topologies) have been extensively studied in [16,17].

In this paper, the impact of the number of delay cell stages (ranging from 3 to 11) used in differential ring VCO (DR-VCO) topology in reducing phase displacement is analysed using classical small signal model and feedback theory. The VCOs were designed using 90 nm CMOS process for a constant target frequency of 2.6 GHz and simulated in Keysight's Advanced Design System (ADS). To further validate the analysis and simulation results, the DR-VCOs of a different number of stages have been tested using type II 3rd order Charge pump based PLL (CPLL) testbed. As part of the validation, design of a third order CPLL for fast settling time post SET is considered in this paper.

Section snippets

Differential ring oscillator

The four-stage differential delay cell-based ring oscillator topology with inversion in the third stage for oscillation to occur (no inversion required for the odd number of stages) is shown in Fig. 1a. Unlike, single ended current starved delay cell based VCO which need to have an odd number of stages, the differential delay cell of the DR-VCO can have odd or even number of stages. The differential delay cell shown in Fig. 1b is used for analysing the behaviour of DR-VCO and DR-VCO based CPLL.

Introduction to PLL

PLL produces a stable output clock that is synchronized to the input reference clock. Therefore, in the lock state, the phase difference between divider output signal and the reference signal should be constant. Based on phase error φe = φref - φdiv between reference signal φref and divider signal φdiv, Phase Frequency detector (PFD) activates UP or DOWN switches of the charge pump. The CP sources a pump current of Icp (if UP = 1) or sinks a pump current of Icp (if DOWN = 1) to/from Loop Filter

Simulation results for SET tolerance of DRO

To evaluate the performance of differential VCOs of a different number of stages (ranges from three to eleven) in the PLL under SET environment, all the differential VCOs have been designed to have same operating frequency and VCO gain. Also, for fair comparison, the output swings of each differential delay cells are designed to have almost same value (10% variation in swing). An example of the transient change in control voltage of the VCO and output signal frequency following radiation strike

Conclusion

SET tolerance study for differential ring VCO is studied using small signal analysis and simulation for a different number of delay cell stages (varies from three to eleven). The Number of stages used in DR-VCO has a considerable impact on phase displacement produced by the SET hit. Phase displacement decreases with increasing number of stages in the stand-alone DR-VCO. DR-VCOs with delay cell stages varying from 3 to 11 with similar tuning range were designed to operate at 2.6 GHz and have

References (25)

  • J. Wu et al.

    A 3-band CMOS DTV tuner IC for DVB-C receiver

    IEEE Trans. Consum. Electon.

    (2007)
  • T.D. Loveless et al.

    A hardened-by-design technique for RF digital phase-locked loops

    IEEE Trans. Nucl. Sci.

    (2006)

    • Cited by (10)

    • Measurement and evaluation of the Single Event Effects of high-performance SerDes circuits

      2021, Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
      Citation Excerpt :

      It is also possible that the impact of ions on the CPLL or other functional modules of the TX is greater than on those of the RX. Therefore, the reinforcement of the CPLL circuits must be considered in the design of a radiation-tolerant SerDes for application-specific integrated circuits (ASICs) because of the low SEU threshold, highly saturated cross-section, and huge influence on function [17–21]. In addition, a Quad phase-locked loop (QPLL) can also be selected to provide faster clock signals for the TX and RX of a Quad than those of a CPLL, so it can be inferred that a radiation-hardened QPLL is also necessary for ASIC design.

    • Single event transient hardened delay cell for a differential ring VCO

      2020, Microelectronics Reliability
      Citation Excerpt :

      Experimental determination of phase-dependent sensitivity of the single event effects (SEEs) of high-speed PLL circuit was presented in [19] using periodic laser injection. In [20], it was shown that increasing the number of stages in DR-VCO reduces the phase perturbation and erroneous cycles caused by ion hit in standalone VCO and as part of a PLL. However, increasing the delay stages increases power consumption and area.

    • A novel single-event-hardened charge pump using cascode voltage switch logic gates

      2018, Microelectronics Reliability
      Citation Excerpt :

      Furthermore, mitigation possibilities for SETs occurring other modules in PLL are also be considered. Since the SET responses in VCO and DIV are both the phase displacement of the output signal [5,9,11,22], a 560° phase displacement corresponding to LET of 50 MeV·cm2/mg [22] was added to the reference clock to observe if the RHCP can mitigate the SETs occurring at VCO and DIV. As shown in Fig. 11, ΔVc of the RHPLL is 172 mV, 24.6% smaller comparing with unhardened PLL and the time for RHPLL to recover to lock state is 620 ns, approximately 8% shorter comparing with the unhardened PLL.

    • Low Power Radiation-Hardened Current-Starved Ring Voltage-Controlled Oscillator

      2023, SSRN

    • A Single-Event-Hardened Scheme for Ring Oscillator Applied to Radiation-Resistant PLL Microsystems

      2023, Micromachines

    • Low Power Radiation-Hardened-By-Design Based Voltage-Controlled Oscillator for Phase-Locked Loop Application

      2023, SSRN
    View all citing articles on Scopus
    View full text
    © 2018 Elsevier Ltd. All rights reserved.