SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices
Introduction
Polycrystalline silicon (Poly-Si) channel has been widely applied on flash devices for three-dimensional (3D) memory integration such as pipe-shaped bit cost scalable (P-BiCS) [1], terabit cell array transistor (TCAT) [2] and vertical gate (VG) [3] due to the fast increasing demand of non-volatile memory market. Among these 3D architectures, horizontal channel and VG are likely better structures [4] to increase device density. Since junction dopants in 3D memory devices are difficultly formed, junctionless (JL) channel was proposed to omit junction formation by simultaneously doping source/drain (S/D) and channel into the same type. Recently, gate-all-around (GAA) configuration was widely applied on charge-trapping (CT) flash devices, indicating that operation characteristics can be much improved by GAA configuration [5,6]. Furthermore, stacked trapping layer such as Si3N4/high-k was reported to enhance the operation speed and reliabilities of CT flash devices [7,8]. However, the thermal budget of fabrication process should be reduced and carefully controlled due to the increasing vertical layer of channel architecture and applications of high-k dielectrics in 3D flash devices. A high temperature deposition process using a furnace should be replaced by a low temperature deposition such as Inductively Coupled Plasma Chemical Vapor Deposition (ICP-CVD) for 3D architecture [9]. However, a plasma CVD system may cause anisotropic deposition on GAA configuration, which then affects the operation characteristics of CT flash devices. Therefore, the SiO2 tunneling and Si3N4/HfO2 stack trapping layers formed with low temperature (LT) processes on operation characteristics of CT flash device with horizontal GAA and Ω-gate nanowire (NW) configurations were studied in this work.
Section snippets
Device fabrication
Poly-Si GAA and Ω-gate NW devices were fabricated on 6-inch Si wafers. For GAA devices, a 100-nm thick SiO2, a 50-nm thick Si3N4 buried layer, a 100-nm thick tetraethoxysilane (TEOS) oxide and a 100-nm thick in-situ n-doped poly-Si were sequentially deposited by a low pressure chemical vapor deposition (LPCVD). Then, the active regions of suspending poly-Si channels for all samples were formed by the following processes. In-situ poly-Si layer was patterned and etched to form four mesa stripes
Results and discussion
Fig. 2 shows transmission electron microscopy (TEM) images of (a) LT-NW, (b) HT-NW, (c) LT-GAA, and (d) HT-GAA devices. The widths of poly-Si channels for Ω-gate NW and GAA devices are about 10 and 13 nm, respectively. The thicknesses of SiO2 tunneling and Si3N4 trapping layers at the channel bottom of LT-GAA device are smaller than those of others due to the anisotropic deposition and worse step coverage of dielectrics formed by ICP-CVD.
Fig. 3 shows drain current (Id) versus gate voltages (Vg)
Conclusions
The effects of SiO2 tunneling and Si3N4/HfO2 stack trapping layers formed with LT processes on CT flash devices with GAA and Ω-NW configurations were investigated. A faster operation speed and a larger memory window are achieved by GAA configuration. However, the reliability characteristics such as retention and endurance of GAA JL CT flash devices formed with LT processes are worse than those with HT ones. The worse step coverage of dielectrics deposited with LT processes at the bottom of
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Operation Characteristics of Gate-All-Around Junctionless Flash Memory Devices with SiN/ZrO-Based Stacked Trapping Layer
2020, IEEE Transactions on Electron Devices