Investigation and impact of LDD variations on the drain disturb in normally-on SONOS NOR flash device
Introduction
Silicon-oxide-nitride-oxide‑silicon (SONOS) and floating gate (FG) memory are popular in nonvolatile memory (NVM) technologies. FG memory is widely used in many fields due to its high program efficiency. However, its extrinsic charge loss and stress induced leakage current (SILC) [1] limit its applications in high reliability and security fields. Additionally, the thickness of bottom oxide becomes the bottleneck of the FG memory technology evolution as device dimensions shrink [2,3]. Its counterpart, SONOS memory technology, has recently attracted increasing interest [4] for various advantages. SONOS memory requires lower power consumption for the Fowler-Nordheim program/erase operations [5,6]. Commercially, the greatest merit is cost effective with fewer masking layers owing to its better compatibility with CMOS process [7,8]. Furthermore, lower operation voltage relaxes the design complexity of the peripheral circuit [9,10]. Compared with FG memory, many trapping layers are optional for SONOS memory, such as oxynitride layer which can operate at lower voltage and higher temperature [11] without compromising reliability. Moreover, strong radiation tolerance and superior reliability performance [12] of SONOS flash enables its application in radiation environment such as space workstation [2].
This work is based on 2-transistor (2-T) structure SONOS flash memory device. In our previous work [13], we clarified that the distribution of drain disturb (DD) is non-localized. However, the correlation between the drain disturb and stress time needs to be further studied. Additionally, qualitative E-Field simulation in our previous work is much larger than calculated value given by [14].where VG is the applied gate voltage, VFB is the flatband voltage, ∅s is the TO/Silicon surface potential, and teq is the equivalent oxide thickness (EOT). Therefore, transient simulation is applied to elaborate the DD characteristics. It simulated the charge transport, distribution, and tunneling effects in dielectrics.
In this work, it is also demonstrated that LDD optimization is critical and imperative for better tradeoff between the on-state current and DD immunity in this flash device. For short channel length device, LDD is essential for suppressing short-channel effects (SCEs), increasing breakdown voltage [15] and the transfer current, and reducing the impact ionization [16,17]. However, it is confirmed that LDD degrades DD immunity of device in this paper. In consequence, we fully investigated and optimized LDD with considerations of both high DD immunity and large on-current. LDD implantation was also chosen to reveal the principle of process optimization for its high impact on DD.
This work clearly demonstrates the DD distribution and also elaborates the influence of LDD variations on DD by experiments and simulations. In Section 2, details about device, operating bias stress, and models for device simulation are presented. Subsequently in Section 3, drain disturb properties are demonstrated. The impact of LDD on disturb is also discussed and an optimized LDD recipe is proposed and verified for both high DD immunity and large on-current. Finally, we present a conclusion about this paper.
Section snippets
Device and measurement/simulation details
Normally-on and LDD-based 2-T SONOS device and its array are illustrated in Fig. 1, Fig. 2, respectively. A single bit consists of a memory transistor (SONOS) and a select gate (SG) transistor. As illustrated in Fig. 1, a common region is located between SONOS and SG, and thus a single bit has five terminals (WL, WLS/G, SL, BL/D, and B). G and D represent gate and drain terminals of SONOS field effect transistor (FET), respectively.
During the simulation, Sentaurus Process and Device tools are
Drain disturb characteristics
The programming condition is labeled in Fig. 2. After 5 P/E cycles in order to achieve steady program and erase state, simulated trapped electron charge density in the nitride layer are illustrated in the Fig. 3. Clearly, it was noted that trapped charge in the nitride is uniformly distributed along the channel after programming.
As shown in Fig. 4, with DD-bias, we found that vertical TO electric field (E-Field) gradually decreases along the drain-source direction and a peak value exists near
Conclusion
In this paper, we fully investigated drain disturb characteristics and the impacts of LDD on drain disturb, which have been demonstrated by experiments and simulations. It was confirmed that vertical TO E-Filed at channel center has a peak value along with DD stress time, which is attributed to different charge de-trapping rate at channel-inside and drain-side region. Depletion region analysis is presented to illustrate the correlation between DD immunity and process variations. It reveals that
References (20)
- et al.
Study of charge loss mechanisms for nano-sized localized trapping SONOS memory devices
Solid State Electron.
(2014) - et al.
4 - improving embedded Flash memory technology: silicon and metal nanocrystals, engineered charge-trapping layers and split-gate memory architectures A2 - Nishi, Yoshio
- et al.
Hydrogen-induced program threshold voltage degradation analysis in SONOS wafer
Solid State Electron.
(2016) - et al.
A comparative study of charge pumping circuits for flash memory applications
Microelectron. Reliab.
(2012) - et al.
Characterization of SONOS oxynitride nonvolatile semiconductor memory devices
Solid State Electron.
(2003) - et al.
Investigation and process optimization of SONOS cell's drain disturb in 2-transistor structure flash arrays
Solid State Electron.
(2017) An analytic model to estimate the avalanche breakdown voltage improvement for LDD devices
Solid State Electron.
(1985)- et al.
Numerical analysis of poly-TFTs under off conditions
Solid State Electron.
(1997) - et al.
Charge retention in scaled SONOS nonvolatile semiconductor memory devices—modeling and characterization
Solid State Electron.
(1993) - et al.
Thickness dependence of stress-induced leakage currents in silicon oxide
IEEE Trans. Electron Devices
(1997)