Impact and mitigation of SRAM read path aging
Introduction
CMOS technology scaling is well known for causing crucial reliability challenges on electronics reliability [[1], [2], [3]]; e.g., it reduces their lifetime. A general practice in industry is the use of conventional guard-band and application of extra design margins to counteract for the Bias Temperature Instability (BTI) effect. Accurate estimation of such effect is vital for achieving an optimal design. Clearly, an electronic system comprises of various parts; hence, accurate BTI estimation requires to evaluate not only all the various parts of the system, but also the way they communicate with each other, and how they all provide to the complete degradation of the system. For example, when it comes to SRAMs, estimating the effect of BTI by only focusing on the memory array, or by only integrating the individual effects of each components, will lead to optimistic or pessimistic results.
Several publications have investigated the impact of reliability on individual SRAM components. Kumar et al. [4] and Carlson et al. [5] analyzed the impact of negative Bias Temperate Stability (NBTI) on the read stability and the Static Noise Margin (SNM) of SRAM cells. Bansal et al. [6] presented insights on the stability of an SRAM cell under the worst-case conditions and analyzed the effect of NBTI and PBTI (positive BTI). Khan et al. [7] performed BTI analysis for FinFET based memory cells for different SRAM designs using SNM, Read Noise Margin (RNM) and Write Triple Point (WTP) as metrics. Menchaca et al. [8] analyzed the BTI impact on different sense amplifier designs implemented on 32 nm technology node by using failure probability (i.e., flipping a wrong value) as a reliability metric. Agbo et al. [[9], [10], [11], [12]] investigated the BTI impact on SRAM drain-input and standard latch-type sense amplifier design, while considering process, supply voltage, and temperature (PVT) variations in the presence of varying workloads and technology nodes. Rodopoulos et al. [13] proposed and investigated the pseudo-transient atomistic-based BTI model with built-in workloads while considering various supply voltages and temperatures. Other research focused on mitigation schemes. For example, Kraak et al. [14] and Pouyan et al. [15] investigated the mitigation of SA offset voltage degradation by considering periodic input switching. Gebregiorgis [16] investigated a low cost self-controlled bit-flipping scheme which reverses all bit positions with respect to an existing bit.
From the above, we conclude that not much work is published on aging, while taking into account all the memory components and thus their interactions, and the effect of mitigation methodologies on the whole memory. Li et al. [17] studied the lifetime estimation of each individual transistor for the entire SRAM and for various reliability mechanism (i.e., HCI, TDDB, NBTI). However, this investigation did not require the workload, which has been demonstrated to have a large effect on the degradation rates [13, 18, 19]. In our previous work [20], we analyzed the impact of aging in the read path of a 32 nm high performance SRAM design for different workloads. However, the impact of aging on different supply voltages, temperatures, technology nodes, and varying device drive strengths based on BLS, SD, and energy (E) metrics on the memory read path are yet to be explored. In addition, effective mitigation schemes are not proposed. The above clearly shows that an appropriate approach (that accurately predicts the impact of aging, workloads, and PVT) is needed. Hence, this analysis is crucial to help memory designers understand which of the memory parts to focus on during design for an optimal and reliable design.
In this paper, we set up a step towards this, and we propose an accurate method to estimate the impact of Bias Temperature Instability (BTI) on the read path consisting of an SRAM cell and sense amplifier (SA). This enables not only optimal designs (in terms of design margins), but also the development of appropriate design-for-reliability schemes. The proposed method uses the Atomistic Model for aging (which is a calibrated BTI model [21, 22]) and considers the workload dependency (as the aging variations are strongly workload dependent [18, 19]). To measure both the impact of the cell and SA appropriate workloads are defined while using the bit-line voltage swing, SA SD, and energy as metrics. In addition, we analyze different mitigation schemes and their effectiveness.
The rest of the paper is organized as follows. Section 2 provides the SRAM simulation model, and explains BTI mechanism and its model. Section 3 provides the analysis framework and performed experiments. Section 4 analyzes impact of aging on the read path. Section 5 proposes and evaluates the mitigation schemes. Finally, Section 6 and Section 7 discusses the results and concludes this paper, respectively.
Section snippets
Background
This section briefly presents the simulation model; it consists of the critical SRAM components in the read path. Finally, it discusses the BTI mechanism and its model.
Analysis framework
This section presents the analysis framework and the conducted experiments.
Experimental results
This section, presents the analysis results of the experiments mentioned in the previous section.
Mitigation schemes
In the previous section, we observed that BLS and SD may heavily be impacted by BTI. In this section, we investigate two mitigation techniques, i.e., increasing the cell's and the SA's drive strengths. This drive strengths only applies to the pull down transistors for both cell and SA (i.e., Nom.DS denoting normal sized transistors, 125%DS denoting 125% larger transistors, and 150%DS denoting 150% larger transistors). Note that the pull up transistors are not affected that much due to bit line
Discussion
The memory cell and SA robustness are vital for the overall design of memory systems. Below some interesting observations are made.
The obtained results clearly show that for the considered SRAM design the cell has a low impact and that the SA is the major component responsible for the read path timing degradation, even under different voltages, temperatures and technology nodes. Therefore, this information can be used by the designers to optimize the design margins of the cell. One possible
Conclusion
This paper investigated an accurate technique to estimate and mitigate the impact of Bias Temperature Instability (BTI) on the read path of a memory design while considering various degrading components i.e., Cell only, SA only, and Combined (i.e., cell and SA), and for different workloads, supply voltages, temperatures and technology nodes. Hence, the proposed methodology for the entire read path degradation analysis is an interesting case study as it allows for a better understanding of the
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Application-aware aging analysis and mitigation for SRAM Design-for-Relability
2022, Microelectronics ReliabilityCitation Excerpt :We demonstrate the method by analyzing SA and SRAM cell aging for various application workloads, temperatures and supply voltages. The presented results show (1) that realistic workloads are an important factor for the accurate prediction of aging, (2) that the aging of SAs was often overestimated in previous work [5,15] (3) that, depending on the cell sizing, both SA and SRAM cell aging have a significant contribution to the degradation of the read-path and (4) that, non-intuitively, aging in the SA's control signals counteracts the bit line swing degradation caused by the cell aging to some extent leading to minor performance improvements. Detailed analysis shows the cause of this positive aging effect.
Analysis of SRAM metrics for data dependent BTI degradation and process variability
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