Source engineering on ruggedness and RF performance of n-channel RFLDMOS
Introduction
While p-channel LDMOS is competent for switching applications [8], n-channel LDMOS is usually used in RF power applications. RFLDMOS FETs are widely used in transceivers, broadcasts, radar, base stations as power device, for its cost, different operation voltages, and wide frequency band in recent decades [15].
Nowadays, obtaining good RF performance and outstanding reliability at the same time becomes the most important and challenging task for RFLDMOS design. These factors, such as frequency bandwidth, gain, output power, efficiency, noise, non-linearity, and so on, are selectively used to assess the performance of different RF applications. Reliability issues of MOSFETs, such as HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability), had been analyzed and discussed in [[16], [17], [18]]. And ruggedness which indicates the ability of a device withstands unusual electrical condition without degradation [13] is also momentous reliability factor of RFLDMOS [[5], [6], [7], 10, 13].
In order to study the ruggedness of DUTs (Device Under Test), many test methods had been introduced, such as TLP test on wafer and packaged level [1], ESD (Electro-Static Discharge) sensitivity test and VSWR susceptibility test for RF/microwave devices on package level, and so on. ESD sensitivity test is a kind of voltage zapping test for packaged DUT, after each zap the system will estimate whether the DUT fail or not by verifying its characteristic curve, and finally get the ESD sensitive voltage which is classified in different levels. On the other hand, TLP system can extract every current and voltage during each zap, and these values can be plotted as I-V curve. TLP test standard [2] and industrial TLP apparatus are available to researchers all around the world. Though TLP I-V curves had been studied a lot in ESD structures [3, 4] and LDMOS [[5], [6], [7], [8]], different curve forms among them had seldom been analyzed deeply in terms of different structure engineering.
Structure engineering is a general method of optimizing the characteristics of LDMOS. When LDMOS used in ESD protect units, source-side and drain-side SCR (Silicon Controlled Rectifier) structures can bring it into latch-up state and conduct large current without destruction [19]. In RFLDMOS, structure engineering has been done carefully because unexpected parasitic capacitors degrade key parameters, such as transconductance, cut-off frequency, and so on [20]. So, PBL source-side engineering, which has small effect on RF performance, is applied in our RFLDMOS.
The aim of this paper is interpreting ESD failure mechanism of RFLDMOS FETs with and without source engineering during ESD event and estimating their overall performance. In this paper, the state-of-art RFLDMOS FETs with and without source engineering and TLP test principle will be introduced in section II. Then, equivalent circuit and key parameters will be modeled and calculated in section III. Next, two kinds of test curves will be analyzed with equivalent circuit models and key parameter models, also semiconductor physics theories will be adopted to interpret these phenomena in section IV. In section V, source/load-pull test and VSWR susceptibility test are used to study the RF performance of DUTs.
Section snippets
RFLDMOS structure and TLP system for ruggedness test
According to RESURF (REduced SURface Field) technique [7], LDMOS has been designed with a low doping N-type area in the drain side to withstand high breakdown voltage. In Fig. 1, a half of one single finger's cross-sections, with and without source engineering, has been illustrated. Unlike using LOCOS (LOCal Oxidation Silicon) and extending gate to adjust surface field, Faraday shield, which is connected to source metal with metal lines and through the via, has the same function. Moreover,
Modeling
Equivalent circuit and approximation calculation are used to analyze failure mechanism of DUTs during ESD progress. Fig. 3 is the parasitic equivalent circuit of LDMOS. The equivalent circuit is like the ones reported in [5, 11]. In this figure, diode DDB withstands high reverse voltage through the total depletion of drift region, CDB depends on the junction of drift region and channel region, and RB is a resistor which comes from channel region connecting to source pad. rc and rb are resistors
TLP test results and analysis
Using 0.18 μm BCD process, with and without PBL devices were fabricated in two different wafers where the PBL implant is the only different procedure. Several devices with different finger numbers had been fabricated, where other parameters kept the same. In addition, another group of DUTs with different PBL dosage also have been fabricated.
RF performance and susceptibility test
In TLP test, the ruggedness of different PBL devices are easy distinguished, but overall characteristics of application cannot be solely evaluated only by it. Beyond TLP test, VSWR measurement is used to estimate the ability of handling mismatch in realistic usage, while source/load-pull is used to assess RF performance. So, the DUTs in Fig. 7 have been packaged into two forms for source/load-pull test and susceptibility test.
Metal packaged DUTs are mounted on fixture, which is connected with
Conclusion
This paper analyzed failure mechanism of state-of-art RF LDMOS with and without PBL source engineering in TLP test, then source/load-pull test and susceptibility test were adopted to estimate DUTs' overall performance. In ESD aspect, PBL source engineering can improve ruggedness a lot. Models are adopted to interpret what happened in DUT during ESD zapping, where RB is the key parameter and it can be quantified to optimize foundry process. In VSWR aspect, PBL source engineering also improve the
Acknowledgements
One author, Hao Li, would like to thank Professor Chuanbin Zeng for his instruction of TLP principles and test, and Jianwei Ren for her discussion of models.
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2019, Tien Tzu Hsueh Pao/Acta Electronica Sinica