Performance-reliability trade-offs in short range RF power amplifier design
Introduction
Short range RF Complementary Metal Oxide Semiconductor (CMOS) transmitters are flourishing in the current Internet of Things (IoT) paradigm for a wide range of applications including health monitoring [1]. In this scenario, critical applications involving this kind of circuits require a conscientious evaluation of reliability at a design stage, exploring trade-offs between performance aspects and expected reliability.
Transistor level reliability hazards have been widely studied to ensure a suitable working lifetime for products along the CMOS technology roadmap. Constant downscaling and increasing electric field in transistors made of time dependent dielectric breakdown (TDDB) [2] and Hot Carrier Injection (HCI) [3] a severe threat to device oxide reliability. But a majority of this research has been focused at the product level for, mostly, digital devices with very large scale of integration. Nevertheless, many efforts have been carried on so far to take reliability models into account to predict and implement on-chip strategies for reliability in RF circuits [[4], [5], [6], [7]], but usually centred on analysis or simulation of a given design instead of incorporating the reliability aspect into a design space or architecture exploration.
In this work, we focus on class A-to-C power amplifiers (PAs) working at 2.455 GHz, fully integrated in a 130 nm RF CMOS technology. We propose a design stage exploration of reliability in terms of the matching resistance at the output, taking into account the trade-offs present during matching network design. TDDB and HCI effects are introduced in the design exploration as the two main reliability hazards for PAs. To evaluate the design approach, a simulation study is performed on different PA designs in SPICE, each with a different output matching network topology, and the trade-offs between reliability and circuit performance are discussed. The remainder of the work is organized as follows: Section 4 revisits the TDDB and HCI models and summarizes the approach applied in this work; Section 5 discusses a design exploration of the trade-offs in PA design taking into account reliability indicators; Section 4 shows the comparative results between PA designs based in reliability aware SPICE simulations; finally, Section 5 draws the conclusions.
Section snippets
Time dependent dielectric breakdown
TDDB is a stochastic phenomenon that has been modelled through percolation theory: the applied electric field and the leakage current through the gate oxide contribute to the build-up of defects until a percolation path is created spanning the oxide, forming a conductive path between the channel and the gate contact. The failure rate is characterized by Weibull statistics and strong power law or exponential voltage acceleration of the time to breakdown [2]. In this framework, circuit modelling
Impact of BD path modeling on PA performance
Modelling of the BD path between gate and source or gate and drain can show very different sensitivities in terms of circuit performance. This can be explained by the impact of such resistors on the RF performance of the device. While RGD has a direct impact on the transducer gain, RGS impacts introducing an impedance mismatch at the input of the circuit, without any impact on the transducing characteristics. Therefore, same performance degradation of the PA is observed for slightly higher
Reliability simulations of PA design cases
Transistor degradation models [2, 8, 9, 13] were introduced into a Spectre RF simulation flow. The circuit is simulated under a periodic steady state (pss) for different elapsed times of continuous operation. In each time instant, the drain and gate voltage waveforms are obtained and used to calculate the degradation parameters to be introduced into the design and used for the simulation of the next time step. The general simulation procedure here described is represented in the flow chart of
Conclusions
In this work, a design perspective for reliability of low power CMOS RF PAs is introduced. Results show a reliability enhancement for lower drain voltages at constant output power, but with a strong trade-off with matching network efficiency for on-chip implementations. This trade-off can be performed, at constant output power, by reducing the RF drain resistance. Finally, the importance of a SPICE implementation to simulate device lifetime was highlighted by the fact that circuit degradation
Acknowledgments
The research leading to this work was funded by the following institutions: in Argentina, UTN.BA under projects EIUTIBA4395TC, EIUTIBA4764TC and UTNI3856, CONICET under project PIP11220130100077CO and MINCyT under project PICT2013/1210; in Uruguay, Universidad De La República under article 57 and the 720 program.
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2020, Microelectronics ReliabilityCitation Excerpt :The schematics of a typical class A-to-C PA including a simple bias block is depicted in Fig. 1a and b. Considering that the drain is operating at a high selectivity QD (i.e. the output matching networks presents a high attenuation for all but the tuning frequency fc), the output power is given by Pout = VDRF2/2RD, being RD the converted impedance towards the drain. From a reliability perspective, the peak drain voltage VDRF has a strong impact on HCI degradation [12]. The effects of HCI on a fully integrated, 2.455 GHz, 0 dBm output power CMOS RF PA fabricated in a 130 nm technology, like the one from Fig. 1a, are shown in Fig. 2.
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