TCAD modeling for reliability

doi:10.1016/j.microrel.2018.06.109

Microelectronics Reliability

Volumes 88–90, September 2018, Pages 1083-1089

https://doi.org/10.1016/j.microrel.2018.06.109 Get rights and content

Highlights

•
TCAD simulations are necessary for the understanding of reliability issues.
•
NBTI and hot-carrier degradation is analyzed with Sentaurus Device.
•
The row hammer effect in DRAM is illustrated with Process Explorer.
•
Chip-package interactions and thermo-mechanical reliability issues are studied with Sentaurus Interconnect.

Abstract

Technology Computer Aided Design (TCAD) tools can be used to effectively study and analyze a multitude of reliability issues in semiconductor devices. In the following article, we first describe Negative-Bias Temperature Instability (NBTI), which is one of the most severe reliability issues. Using the Reaction-Diffusion (RD) model for simulating the NBTI effect, we show that the simulated threshold voltage degradation agrees well with measured data. Based on the simulation results, we propose an on-chip heater to enhance recovery and revert the NBTI degradation. Next, we discuss how to apply the Hot-Carrier Stress (HCS) model to analyze hot carrier degradation in FinFET. We show that the threshold voltage shift agrees well with experiment and use the HCS model for the simulation of breakdown voltage walkout in a LDMOS transistor. Then, we apply process emulation to better understand modern DRAM structures and illustrate the row hammering reliability issue. Finally, we demonstrate a multi-level sub-modeling methodology for chip to package interaction (CPI) and apply the method to study the effect of wafer bending on the reliability of re-distribution layers (RDL).

Introduction

Technology Computer Aided Design (TCAD) tools, such as Synopsys Sentaurus™ TCAD, are well established for modeling semiconductor fabrication processes, and device operations. Process simulation includes the modeling of process steps, such as implantation, diffusion, oxidation, etching, deposition, and mechanical stress distribution. Device simulation considers the electrical and thermal behavior of devices, such as current flow and heat generation. Using TCAD, many reliability aspects can be modeled [1].

In the following sections, we describe Negative-Bias Temperature Instability (NBTI), hot carrier degradation, row hammering in DRAM memory cells and mechanical stress modeling.

Section snippets

Negative bias temperature instability

Negative-Bias Temperature Instability (NBTI) is still one of the most severe reliability issues [[2], [3], [4], [5]]. NBTI means that the threshold voltage (V_TH) of p-MOSFETs becomes more negative after ON-state operations (|V_GS| > |V_TH|), resulting in lower drain current over time. The effect is exacerbated at elevated temperature when there is self-heating in the device.

Two leading models for NBTI, namely the Reaction-Diffusion (RD) model [2, 3] and the Defect-Centric (DC) model [4], have

Hot carrier degradation

Hot carrier degradation is still one of the key challenges for circuit reliability, especially in analog and mixed-signal design. High electrical current and high electric fields can create additional interface traps which lead to threshold voltage shifts and mobility degradation through scattering at trapped interface charges. For low power SOC (Systems on Chip) and mobile applications, FinFETs are used for the 22 nm node and below. Especially, FinFETs for input and output (I/O) suffer from

Row hammer effect in DRAM

In this section, we discuss row hammering, which has become a major reliability (and security) issue for sub 30 nm node dynamic random-access memory (DRAM).

Scaling of the cell transistors has been one of the main driving forces in DRAM. To overcome retention time degradation and short-channel effects, the design of cell transistors has evolved from planar shape to a saddle-fin structure [18].

Due to the complex topology of modern cell architectures, we used Synopsys' Process Explorer to emulate

Thermo-mechanical reliability

Chip to package interaction (CPI) has been a major concern for advanced silicon technologies with large die size, lead free bumps, and low k dielectrics packages. Recent studies show that the CPI effect is further enhanced during the board assembling process step [20].

Because stresses are accumulated from all fabrication, packaging, and assembling steps, process simulations are required to track stress generation for accurate reliability evaluation.

A TCAD multi-level sub-modeling methodology

Conclusion

Due to the complexity of modern technologies, TCAD simulations are instrumental and necessary for the understanding of device behaviors, especially for the qualitative and quantitative understanding of the physics of reliability issues.

In this article, we illustrated the use of TCAD for the explanation of NBTI and hot-carrier degradation, discussed the row hammer effect in modern DRAM cells, and described how TCAD can be used to analyze chip-package interaction and thermo-mechanical reliability

References (23)

S. Mishra
TCAD-based predictive NBTI framework for Sub-20-nm node device design considerations
IEEE TED
(Dec. 2016)
P. Pfaeffli
TCAD for reliability
Microelectronics Reliability
(2012)
S. Mishra
Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials
T. Grasser
The paradigm shift in understanding the bias temperature instability: from reaction-diffusion to switching oxide traps
IEEE TED
(2011)
J.H. Stathis
The physics of NBTI: what do we really know?
Sentaurus™
Device User Guide Version N-2017.09
(September 2017)
N. Parihar
Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in RMG HKMG SiGe FDSOI p-MOSFETs and p-FinFETs
(2018)
H.Y. Wong
FinFET NBTI degradation reduction and recovery enhancement through hydrogen incorporation and self-heating
H.Y. Wong
On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits
(2018)
C.-H. Jan
A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 μm² SRAM cells, optimized for low power, high performance and high density SoC products

E.-A. Chung

Investigation of hot carrier degradation in bulk FinFET

Cited by (8)

Geometric advection and its application in the emulation of high aspect ratio structures
2021, Computer Methods in Applied Mechanics and Engineering
Citation Excerpt :
This method is referred to as geometric advection. This approach has already been applied successfully with voxel-based material representations for several years [26,28]. Usually, voxels would be defined on a regular grid, just like the LS, and given a numerical identifier to denote which material they represent.
The ability to simulate the processes required to fabricate advanced microelectronic structures, commonly referred to as process technology computer aided design (TCAD), is essential for the semiconductor industry. It aids in the design and development of modern integrated circuits at low cost. Ongoing demands of high efficiency and simplicity lead to the development of process emulation techniques, which describe the effect of a fabrication step by using only the geometric properties gathered from experimental data or extracted from physical simulations. However, the accuracy of current emulation models is limited by their strong reliance on explicit surface representations, while traditional algorithms employing implicit surfaces, such as the level set, can frequently suffer from numerical limitations. A novel geometric advection algorithm for microelectronic process emulation is presented, which advances a level set surface over large distances in a single simulation step. It combines the advantages of explicit surface representations, such as fast access to surface data and efficient sorting, and the robustness of implicit surface representations. Furthermore, calculations are performed directly in the level set avoiding costly conversions to explicit surfaces. The performance and applicability of the algorithm to modern processes is demonstrated by emulating the fabrication of several high aspect ratio structures. Due to the almost universal applicability and computational efficiency of the presented geometric advection algorithm, it provides an entirely new way of emulating microelectronic fabrication processes and presents a promising alternative to long-standing and commonly used techniques.
Modified Hurkx band-to-band-tunneling model for accurate and robust TCAD simulations
2020, Microelectronics Reliability
Citation Excerpt :
Reducing power consumption while increasing computing performance has been the main thrust to continue Moore's Law in the recent decade and is expected to continue [1]. It is therefore very important to model leakage mechanisms accurately in Technology Computer Aided Design, which has been used extensively by the industry to predict and design the next generation transistors [2]. One of the main leakage mechanisms in modern transistors is Band-To-Band-Tunneling [3], in which electron from valence band tunnels through the bandgap to conduction band, resulting in a generation of electron-hole pair under high electric field.
Band-to-Band Tunneling (BTBT) is a non-local process and is responsible for some of the major leakage mechanisms in transistors such as Gate Induced Drain Leakage (GIDL). It is therefore important to include BTBT in Technology Computer Aided Design (TCAD) simulations to properly capture the leakage current. However, due to its non-local nature, BTBT simulation is computationally intensive. Local BTBT models such as Hurkx model can reduce the computation burden but often underestimate the leakage current at large bias. A new modified Hurkx BTBT model for homojunction devices is proposed and showed to match non-local BTBT model well in diode leakage and transistor GIDL simulations. Compared to non-local BTBT model, using the modified Hurkx model, the simulation speed is increased by >6 times in a 3D FinFET I_DV_G simulation with GIDL.
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems
2024, arXiv
Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs
2023, IEEE Journal of the Electron Devices Society
A Case for Transparent Reliability in DRAM Systems
2022, arXiv
ENABLING EFFECTIVE ERROR MITIGATION IN MEMORY CHIPS THAT USE ON-DIE ERROR-CORRECTING CODES
2022, arXiv

View all citing articles on Scopus

View full text

TCAD modeling for reliability

Highlights

Abstract

Introduction

Section snippets

Negative bias temperature instability

Hot carrier degradation

Row hammer effect in DRAM

Thermo-mechanical reliability

Conclusion

IEEE TED

TCAD for reliability

Microelectronics Reliability

Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials

The paradigm shift in understanding the bias temperature instability: from reaction-diffusion to switching oxide traps

IEEE TED

The physics of NBTI: what do we really know?

Device User Guide Version N-2017.09

Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in RMG HKMG SiGe FDSOI p-MOSFETs and p-FinFETs

FinFET NBTI degradation reduction and recovery enhancement through hydrogen incorporation and self-heating

On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits

A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 μm2 SRAM cells, optimized for low power, high performance and high density SoC products

Investigation of hot carrier degradation in bulk FinFET

A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 μm² SRAM cells, optimized for low power, high performance and high density SoC products