Design of approximate-TMR using approximate library and heuristic approaches

Highlights

• The genetic algorithm approach to build approximate circuits has a high computational cost.

• The heuristic approach has a low computational effort, taking just few minutes to generate approximate circuits.

• The heuristic approach achieves a good balance between error rate and area when compared to the genetic approach.

• The heuristic approach has a good advantage against the worst possible circuits in the population.

Abstract

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then choose the gate transformation based on the bits difference. Experimental results compare the proposed new approach with another state of the art technique that uses approximate gate libraries with genetic algorithm showing a good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.

Introduction

Technology scaling poses an increasing challenge to hardware reliability. Circuits manufactured on advanced technologies are more susceptible to errors, mainly as a consequence of the shrinking of transistor dimensions and the increased integration density [1]. The most important cause of soft errors is the interaction of energetic particles with the silicon. When a particle hits a circuit node, the collected charge produces a transient voltage perturbation at the node. If the affected node is a memory cell or latch, a change of state may happen, which is known as Single-Event Upset (SEU). If a combinational node is affected, it is originated a transient voltage pulse known as a Single-Event Transient (SET), which may be propagated through the logic and eventually may be captured by one or several memory elements. In the past, SEUs were the primary concern. However, for advanced technologies, SETs are becoming very relevant too.

Fault mitigation techniques able to mask soft errors require redundancy and majority voters. Triple Modular Redundancy (TMR) is a well-known technique, which provides excellent concurrent masking capability. However, these techniques introduce considerable overheads regarding both area and power consumption. Within this context, approximate circuits have recently emerged as an alternative approach for building partial TMR solutions. An approximate logic circuit is a circuit that performs a different but closely related logic function to the original circuit. As it is not required to match the original circuit exactly, the approximate circuit can be smaller, but it can still be used as replicas in the TMR to be voted at the majority voter and consequently mask faults. An efficient approximation provides high fault tolerance with a good compromise in area and power. The generation of optimal approximate TMR (ATMR) circuits for any given design is a challenging problem.

Several techniques for approximate circuit generation already exist in the literature. They range from BDD manipulation [2], cube selection [3, 4], testability driven approaches [5, 6] and genetic algorithms [7]. In a past work [8], we proposed the use of two approaches, approximate libraries (ApxLib) and MOOGA (Multi-Objective Optimization Genetic Algorithm), to generate Approximate Triple Modular Redundancy (ATMR) designs optimized for area and fault masking. However, the scalability of the approach started to become a problem, i.e., the computational effort needed to generate good results is too high for large circuits. It can take few weeks to generate ATMR designs for circuits composed of few hundred gates. This paper proposes the use of the approximate library technique with heuristics to build approximations in a faster and deterministic way. Testability and observability measures guide the creation of an approximate version of the circuit. Using this technique, ATMR solutions can take around a minute instead of hours and results show that in some cases, a good tradeoff between area overhead and fault masking can be achieved.

The rest of this paper is organized as follows. Section 2 introduces the main concepts of approximate logic circuits applied to fault mitigation. Section 3 addresses the approximation library approach (ApxLib) and how it generates approximate circuits. Section 4 presents the experimental results.