Elsevier

Nano Communication Networks

Volume 1, Issue 3, September 2010, Pages 224-231
Nano Communication Networks

Voltage-controlled nano-addressing for nanosystem communication

https://doi.org/10.1016/j.nancom.2010.10.002Get rights and content

Abstract

An outstanding challenge for realizing a nanosystem is nano-addressing, i.e., how to precisely access a nanoscale wire in an array for communication between a nanosystem and the outside world. Existing nano-addressing methods are based on implementation of binary decoders, which requires unrealistic precise layout control in nanotechnology. Presented in this paper is a voltage-controlled nano-addressing scheme, which differentiates each nanoscale data line by its electrical parameters (e.g., voltages), instead of requiring unique physical structures. As a result, the proposed voltage-controlled nano-addressing scheme enables bottom-up self-assembly and aggressive scaling of nano-addressing circuits with the rest of a nanosystem. A novel nano-addressing circuit includes two address lines which form resistive voltage dividers, and provide gate voltages for two rows of transistors which gate the nanoscale data lines. For two proposed nano-addressing metrics, resolution and accuracy, the proposed circuit achieves single data line resolution by applying high voltage drops to the address lines or by deploying high subthreshold slope transistors, while an adaptive addressing method achieves addressing accuracy only depending on the uniformity of the address lines, and external time domain variations. SPICE simulations based on compact CNFET models demonstrate the effectiveness of voltage-controlled nano-addressing.

Introduction

While silicon-based technology is rapidly approaching its end [1], recent developments in nanotechnology have led to successful fabrication of a number of nanometer-scale devices, for example, resonant-tunnel diodes (RTDs) [24], molecular bistable devices [20], carbon nanotubes (CNTs) and carbon nanotube transistors (CNFETs).

Among various nanometer-scale devices, carbon nanotubes and carbon nanotube transistors are some of the most promising candidates for the building blocks of next-generation VLSI systems. Carbon nanotubes form excellent nanometer-scale interconnects due to their extraordinary electrical current-carrying capability, thermal conductance, and mechanical stress [17], [25]. MOSFET-like carbon nanotube based field effect transistors (MOSFET-like CNFETs) are unipolar devices behaving the same way as the existing MOSFETs, and are ideal for building nanoelectronic circuits in the same style as the current CMOS circuits. Further, band-to-band tunneling carbon nanotube field effect transistors (T-CNFETs) have the potential to achieve ultra-high on–off current ratio and subthreshold slope, and are ideal as the building blocks of next-generation ultra-low-power and high-performance circuits [21].

These newly developed nanoscale devices provided great opportunity for VLSI circuits to continue scaling in a post-silicon era based on these nanometer-scale devices. On the other hand, nanocircuit design and nanosystem integration techniques must be developed and overcome a number of unprecedented challenges to realize nanosystems.

As the minimum layout feature size becomes smaller than the lithography light wavelength, traditional lithography based manufacturing process can no longer achieve satisfiable resolution, and this leads to significant process variations. Resolution enhancement and other design for manufacturing techniques become less applicable as scaling continues. On the other hand, nanoelectronic circuits are expected to be based on bottom-up self-assembly based manufacturing processes, for example, molecular beam epitaxy (MBE). Such bottom-up self-assembly manufacturing processes provide regular structures, for example, perfectly aligned carbon nanotubes in a dense array [11].

Further, VLSI technology scaling has led to increasingly prevalent defects and significant parametric variations, including critical dimension variation, dopant fluctuation, electromagnetic emission, alpha-particle radiation and cosmic ray strikes. Such parametric variations cannot be avoided by manufacturing process improvement, and they are inherent at the nanometer scale due to the uncertainty principle of quantum physics.

Consequently, nanoelectronic systems must rely on configurability to achieve (1) functionality based on a regular structure, (2) yield by avoiding prevalent defects, and (3) design optimization (on reliability, performance and power consumption) taking into account parametric variations [23].

The crossbar structure (Fig. 1) is one of the most prominent nanoelectronic architecture candidates [23]. A carbon nanotube crossbar structure can be constructed by piling up dense arrays of perfectly aligned carbon nanotubes. Such arrays have been manufactured in one dimension [11]. At each crossing of two orthogonal nanotubes, a transistor is formed. Such a crossbar structure forms the basis of a nanoscale memory [6], [27]. It also provides a reconfigurable computing platform to achieve nanoscale VLSI systems of manufacturability and reliability [16].

However, an outstanding challenge for realizing such a nanoelectronic system is to precisely address an individual nanoscale wire (e.g., a carbon nanotube) in an array. Designing a nano-addressing circuit is a challenging task, for the following reasons. (1) A nano-addressing circuit can only be based on a simple layout of a regular pattern to enable bottom-up self-assembly manufacturing; a complex layout requires top-down lithography based manufacturing and cannot scale well into the nanometer domain. (2) While providing reconfigurability to the rest of the nanosystem, a nano-addressing circuit needs to rely on reconfigurability to function based on a simple regular structure.

Existing nano-addressing schemes are based on complex layouts and require precise layout control by lithography [8], doping [5], or etching [22], which is highly unlikely to be achieved at the nanometer scale. Due to the presence of prevalent defects and significant process variations, they further exhibit certain levels of randomness [5], [8], [26], which results in unaddressable or undifferentiated nanoscale wires, and requires testing schemes which associate nanoscale wires with addresses.

The contributions of this paper are as follows.

  • (1)

    A novel voltage-controlled nano-addressing circuit in a simple regular structure, which enables bottom-up self-assembly and aggressive scaling of nano-addressing circuits with the rest of a nanosystem;

  • (2)

    evaluation of the proposed voltage-controlled nano-addressing circuit in terms of manufacturability, and two newly defined quantitative metrics: nano-addressing accuracy and resolution; and

  • (3)

    methods to achieve nano-addressing resolution and an adaptive nano-addressing method which achieves nano-addressing accuracy depending only on address line uniformity and external time domain variations.

The rest of this paper is organized as follows. Section 2 gives a brief review of the existing binary decoder based nano-addressing mechanisms. Section 3 presents the proposed voltage-controlled nano-addressing circuit. Section 4 gives its evaluation, and two proposed nano-addressing metrics: resolution and accuracy. Section 5 presents techniques for nano-addressing resolution, and an adaptive nano-addressing method for nano-addressing accuracy. Section 6 gives the SPICE simulation results for the nano-addressing circuit and the adaptive nano-addressing method. Section 7 concludes this paper.

Section snippets

Existing nano-addressing schemes

A nano-addressing circuit provides an interface for communication between a nanoscale system and the outside world, for example, to address an array of nanoscale data lines on the four boundaries of a nanoscale crossbar (Fig. 1). The data lines can be wordlines or bitlines of a nanoscale memory, configuration data I/Os, or primary inputs/outputs of a nanoscale VLSI system. A nano-addressing circuit may serve as an address decoder or a bitline multiplexer in a nanoscale memory, or a

Design

A voltage-controlled nano-addressing circuit is constructed by running at least two microscale address lines orthogonally on top of the nanoscale data lines (Fig. 3). At each crossing of the microscale address lines and the nanoscale data lines, a MOSFET-like field effect transistor is formed. Each data line goes through at least two pass transistors, which are gated by the address lines. The address lines and the data lines form voltage dividers. Applying external voltages to the ends of the

Manufacturability

The primary advantage of a voltage-controlled nano-addressing circuit over the existing binary decoder based nano-addressing schemes is the manufacturability improvement.

The existing binary decoder based nano-addressing schemes require every nanoscale wire to have a unique physical structure to differentiate itself, which is highly unlikely to be achieved in a nanoscale manufacturing process—lithography cannot achieve nanoscale resolution, while bottom-up self-assembly based nanoscale

Adaptive nano-addressing

We now study parametric variations and their effects on the proposed voltage-controlled nano-addressing scheme, and present an adaptive nano-addressing method which cancels the parametric variation effects.

Simulation

We implement the proposed voltage-controlled nano-addressing circuit (Fig. 3) based on carbon nanotubes (CNTs) and n-type MOSFET-like carbon nanotube field effect transistors (CNFETs). We run SPICE simulations based on the Stanford CNFET compact model [2]. The CNFETs are of 6.4 nm gate width and 32 nm channel length, as is given by the Stanford CNFET compact model. External voltages Vl1=Vr2=1V,Vr1=Vl2=0 are applied to the address lines. A voltage drop Vdd=1V is applied to each nanotube data

Conclusion

Voltage-controlled nano-addressing enables bottom-up self-assembly and aggressive scaling of nano-addressing circuits with the rest of a nanoscale system by differentiating each nanoscale wire by its electrical parameters (e.g., voltages), instead of requiring unique physical structures. Single data line resolution is achievable by applying high voltage drops to the address lines or by deploying high subthreshold slope transistors, while the addressing accuracy given by the adaptive addressing

Bao Liu, Ph.D., is an assistant professor in Electrical and Computer Engineering Department at the University of Texas at San Antonio. His work has included VLSI variability and reliability analysis, robust, high-performance and low-power design, nanocomputing architecture, and emerging technologies. He has published over 50 journal articles and conference papers, and received a Best Paper Award in International Conference on Computer Design in 2005, a Best Research Award in UCSD Research

References (28)

  • International technology roadmap for semiconductors,...
  • Stanford cnfet compact...
  • I. Amlani, N. Pimparkar, K. Nordquist, D. Lim, S. Clavijo, Z. Qian, R. Emrick, Automated removal of metallic carbon...
  • J. Chen, C. Klinke, A. Afzali, P. Avouris, Air-stable chemical doping of carbon nanotube transistors, in: Proc. Device...
  • A. DeHon et al.

    Stochastic assembly of sublithographic nanoscale interface

    IEEE Transactions on Nanotechnology

    (2003)
  • X. Duan et al.

    Nonvolatile memory and programmable logic from molecule-gated nanowires

    Nano Letters

    (2002)
  • B. Gojman et al.

    Evaluation of design strategies for stochastically assembled nanoarray memories

    ACM Journal on Emerging Technologies in Computing Systems

    (2005)
  • J.R. Heath et al.

    Molecular electronics

    Physics Today

    (2003)
  • L. Henrard et al.

    Study of the symmetry of single-wall nanotubes by electron diffraction

    European Physical Journal B

    (2000)
  • A. Javey et al.

    High performance n-type carbon nanotube field-effect transistors with chemically doped contacts

    Nano Letters

    (2005)
  • S.J. Kang et al.

    High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes

    Nature Nanotechnology

    (2007)
  • J. Kong et al.

    Alkaline metal-doped n-type semiconducting carbon-nanotubes as quantum dots

    Applied Physics Letters

    (2000)
  • Y.M. Lin et al.

    High-performance carbon nanotube field-effect transistor with tunable polarities

    IEEE Transactions on Nanotechnology

    (2005)
  • B. Liu, A voltage controlled carbon nanotube addressing circuit, in: International Conference on Nano-Networks,...
  • Cited by (0)

    Bao Liu, Ph.D., is an assistant professor in Electrical and Computer Engineering Department at the University of Texas at San Antonio. His work has included VLSI variability and reliability analysis, robust, high-performance and low-power design, nanocomputing architecture, and emerging technologies. He has published over 50 journal articles and conference papers, and received a Best Paper Award in International Conference on Computer Design in 2005, a Best Research Award in UCSD Research Review in 2002, a China ICCAD Best Member Award in 1996, and a China Mathematics Olympiad Honor Medal in 1988. He has served as the chair of an invited session “Emerging Nano-Circuits and Systems” at the International Midwest Symposium on Circuits and Systems (MWSCAS) in 2010, the co-chair of the “Photovoltaic Technology” session at the Asia Symposium on Quality Electronic Design (ASQED) in 2010, and the co-chair of the “Emerging Design and Technology” session at the International Symposium on Quality Electronic Design (ISQED) since 2006.

    Two preliminary reports were published in NanoNets’08 [14] and ISQED’09 [15], respectively. This manuscript presents a detailed and extended description of the proposed voltage-controlled nano-addressing circuit and adaptive nano-addressing method which provides robust communication for a nanosystem in the presence of prevalent defects and significant parametric variations.

    View full text