Review ArticleTowards realisation of mixed carbon nanotube bundles as VLSI interconnects: A review
Introduction
Carbon nanotubes have received remarkable interest in the IC manufacturing industry during the last decade. Due to their extraordinary physical and chemical properties, CNTs are regarded as ideal material for future on-chip VLSI and SoC interconnects in ultra deep sub micron (UDSM) technologies. The existing Cu interconnect technology has reached its peak scaling limits as the grain size decreases with scaling. Hence their resistivity increases and grain boundary scattering occurs. Thus alternative technologies are required to meet the future challenges given by the International Technology Roadmap for Semiconductors (ITRS).
The ever increasing scaling of integrated circuits is making the interconnect technology a critical aspect in VLSI circuits. Novel integration mechanisms like 3D ICs, multi-core ICs, etc. to attain high speeds and miniaturisation to the core, give rise to reliability problems like thermal reliability, crosstalk, electromigration and scattering [13], [26]. As the scaling goes beyond 22 nm, new materials that can achieve good performance and reliability are being introduced. They are quantum wires called carbon nanotubes. They have very large mean free paths up to a few micrometers at room temperatures, high current carrying capacity, resistance to electromigration, high thermal conductivity and ability to conduct at very high frequencies [26].
Single walled carbon nanotubes (SWCNTs) are one dimensional nanowires that are formed by the rolling up of graphene sheets. They are either conducting or semiconducting depending on their atomic structure, called chirality. Multi walled CNTs (MWCNTs), on the other hand, are concentric cylinders of CNTs that have different diameters and varying chiralities. Their unique properties of high electrical and thermal conductivity coupled with high tensile strength, ballistic transport at high frequencies and resistance to electro-migration have made them ideal for future nanoelectronics applications especially as interconnects in ICs and as channel material in FETs. The electrical and structural properties of CNTs were discussed by many authors [21], [34].
In 2002, Cheung et al. [3] have grown CNTs by the CVD method and after analysing by TEM they have shown that the CNTs were basically in bundle form and a mixture of both SWCNTs and MWCNTs. These types of bundles are called mixed CNT bundles [9]. Mixed CNT bundles (MCBs) have received attention lately due to the advantages they have over SWCNTs and MWCNTs. So, it can be seen that interconnects made of mixed CNTs have superior performance and reliability than SWCNTs and MWCNTs.
Many reviews on CNT growth [33], CNT interconnects [26], CNTFET [32], etc. based on SWCNTs and MWCNTs were done. For the first time, we are reviewing the modelling, simulation and performance analysis of mixed CNT bundles. We also discuss the structural properties and hence the factors that govern the performance of mixed CNT bundle interconnects.
The rest of this paper is organised as follows. Section 2 overviews the circuit modelling of CNT interconnects that include SWCNTs and MWCNTs. Then, we discuss mixed CNT bundle technology for VLSI interconnects in Section 3. Modelling of MCB interconnects is done in Section 4. Crosstalk of CNT interconnects is discussed in Section 5. Finally we conclude this review in Section 6.
Section snippets
Overview of CNT interconnect technology
CNT interconnects were modelled based on the Luttinger liquid theory [2]. This theory describes how electrons interact with each other in one dimension. The electron is created by considering an infinite number of excited 1-D plasmons. Physically, this nature of electrons described by circuit modelling is done to extract the DC and impedance parameters of 1D interconnects. Hence the transmission line (TL) modelling was done. SWCNTs are considered as quantum wires and its equivalent TL
Mixed CNT bundle interconnects
In the first 7 years of the last decade, scientists focussed mainly on SWCNT and MWCNT interconnect applications. However, later scientists have proved that realistic nanotube bundles contain both SWCNTs and MWCNTs [45], [19]. A mixed CNT bundle (MCB), hence, is a mixture of both SWCNTs and MWCNTs as illustrated in Fig. 4.
MCBs are considered as large diameter interconnects and possess higher conductance than its counterparts. The impact of tube density, tube distribution, metallic tube ratio,
MCB conductance
Mixed CNT bundle conductance was derived from the total number of shells, shell diameter and number of conducting channels per shell. Conductance was derived as [21] where is the tube count according to ’s, and its distribution is a normal (Gaussian) distribution with a mean diameter and a standard deviation .
The conductance analysis of MCBs provides us with the tube density, tube distribution, metallic tube ratio, inner to
Crosstalk in CNT interconnects
Crosstalk in CNTs occurs between CNTs that are surrounded by one another as well as inside CNT bundles. CNTs are capacitively coupled to each other in a bundle. So, a coupling capacitor is used in CNT equivalent circuits. However, the magnetic inductance in a CNT bundle is found to be negligible compared to the kinetic inductance up to 100 nm bundle diameter after which it will be significant [44]. So, remarkable work was done by Close et al. [4] on a prototype CMOS IC that contains 14 μm long,
Conclusion
This article reviewed the modelling and simulation aspect of mixed CNT bundle interconnects. As technologies like SoCs, NoCs and 3D ICs are emerging, we see that CNT interconnects will become the inevitable choice for IC manufacturers as it is the most promising material for interconnect applications. As performance and reliability will be increased by rigorous modelling and realistic simulation results in future, the time from design to prototyping will be shortened which makes the technology
P. Uma Sathyakam received the B.Sc. Degree in electronics from the University of Kerala, Thiruvananthapuram, Kerala, India, in 2007, and the M.Sc. degree in applied electronics from Bharathiar University, Coimbatore, TN, India, in 2009.
From 2009 onwards, he was pursuing his M.S. (by Research) degree in microelectronics at the School of Electrical Engineering, VIT University, Vellore, TN, India. His research interests include VLSI interconnects, semiconductor devices, carbon nanotube
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P. Uma Sathyakam received the B.Sc. Degree in electronics from the University of Kerala, Thiruvananthapuram, Kerala, India, in 2007, and the M.Sc. degree in applied electronics from Bharathiar University, Coimbatore, TN, India, in 2009.
From 2009 onwards, he was pursuing his M.S. (by Research) degree in microelectronics at the School of Electrical Engineering, VIT University, Vellore, TN, India. His research interests include VLSI interconnects, semiconductor devices, carbon nanotube electronics, physics of carbon nanotubes and related nanoelectronics applications. His current research is based on modelling and simulation of CNT interconnects.
P.S. Mallick, received his M.S degree from the University of Chittagong, Bangladesh and his Ph.D. from Jadavpur University, India. He worked 4.5 years in a Sweden based electronics industry named IAAB Electronics as a Technical Head. He has 10 years of Teaching experience where he led various research teams and developed “Online Lab in Microelectronics”, “Monte Carlo Simulator”, and “Electric Fencer”. His current area of research interest includes nanoscale CMOS, nanoelectronics and VLSI engineering. He has published 38 research papers in different Journals and conferences of International repute and authored a book on Matlab and Simulink. At present he is working for the School of Electrical Engineering, VIT University, Tamilnadu, India, as a Professor. He has received the prestigious Jawaharlal Nehru Scholarship in 1998 for his doctoral research work. He is one of the enlisted technical innovators of India in 2007.