A new efficient design for random access memory based on quantum dot cellular automata nanotechnology
Introduction
Currently, CMOS is the dominant technology in digital field, however, new emerging technologies can be used to improve the performance of it [1], [2], [3], [4], [5], [6]. Many studies to find new substitutes of CMOS circuits have been done. Quantum dot cellular automata (QCA) is one of the emerging nanotechnologies that has many benefits as compared to CMOS technology. It is faster, has denser circuit arrays and consumes low-power [7], [8], [9], [10], [11], [12]. QCA nanotechnology uses the interaction of bi-stable cells which are include four quantum-dots and two excess electrons [13], [14], [15], [16], [17]. It uses positions of electrons to transfer binary information which are determined by Coulomb interaction [18], [19], [20], [21].
One of the most significant subjects in designing any digital system is memory designing that has been attracted high attention [22], [23]. A random access memory (RAM) as one of the important type of memories is designed to store and retrieve the information from any of its internal locations where the needed time for transmitting of information is always same [24], [25]. In QCA, there are two general structures for designing memory cell, line-based, and loop-based [26]. The loop-based RAM cell does not use extra clock zones and it constitutes a pioneering method of designing well-optimized [27], [28], [29]. However, any optimization in the number of cells, delay and efficiency in a scalability way of RAM cell is valuable.
The main aim of this paper is to design the layout of a RAM cell based on the loop structure based on QCA nanotechnology. The proposed loop-based RAM cell is made up of a D-latch as the basic component. This approach provides many advantages, including single-layer implementation, read/write latency improvement and number of cells reduction. In addition, the 1 4 RAM has been designed and simulated to investigate the scalability of the offered RAM cell. The major contributions of this work can be summarized in the following points:
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Proposing a design of loop-based RAM according to the new D-latch;
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Analyzing area consumption, number of cells, and speed of proposed RAM and existing techniques;
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Verifying and proving the validity of the proposed design using QCADesigner tool.
Section 2 gives a very brief review of QCA-based RAM cell layouts. Proposed D-latch-based RAM architecture based on QCA is described in Section 3. QCA layout and the implementation results of the proposed architecture utilizing QCAdesigner are illustrated in Section 4. Also, comparison with other RAM cells is presented in this section. Finally, the conclusion and future work are discussed in Section 5.
Section snippets
Related work
Khosroshahy, et al. [30] have been proposed a new QCA-based RAM cell with set and reset capabilities using a new majority gate. The proposed RAM is designed based on the new five-input majority gate in this paper which includes five inputs and are inserted into a voter part and then the output value is evaluated. But, because of the injection of inverting inputs to the voter stage, the output cell has also a rotated style. Thus RAM design consists of four three-input and one five-input majority
Proposed design
In QCA technology, a loop-based structure is used for the memory cell design. In this mechanism, storage is implemented via circling a bit of data within a closed-loop of QCA cell [34]. D-Latch is one of the main candidates for the design of loop-based structures in RAM cell designs. In this section, a new method for designing D-latch based on [35] is offered which and then it has been employed to design a RAM cell. According to Fig. 1, 2 1 multiplexer has been used as the D-latch by
Simulation results
In this section, the simulation results are reported by describing the simulation tool, the layout of the proposed designs and analyzing their accuracy. Also, the proposed design is compared to traditional similar designs to show the advantage of it.
Conclusion and future works
In this research, a novel loop-based single-layer nano-scale RAM utilizing D-latch for QCA has been presented. The new RAM cell based on loop structure uses D-latch and optimized QCA multiplexer. This design has a simple structure and can be employed for designing QCA circuits with one layer. In addition, a 1 4 RAM structure is implemented utilizing presented one-bit memory cell. The accuracy of the proposed designs is proved via QCADesigner and results showed that RAM cell helps to attain
Dr. Azath Mubarakali has received his Doctorate from Anna University. His research interest includes Network Security, Software Defined Networks, Block Chain Technology, Networking, Wireless networks and Mobile Computing. He completed his Bachelor and Masters from Anna University. He is a member of various Academic committees, External Bodies and Research Divisions. As expertise is less it continues in the various National and International Publications in reputed Journals and international
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Dr. Azath Mubarakali has received his Doctorate from Anna University. His research interest includes Network Security, Software Defined Networks, Block Chain Technology, Networking, Wireless networks and Mobile Computing. He completed his Bachelor and Masters from Anna University. He is a member of various Academic committees, External Bodies and Research Divisions. As expertise is less it continues in the various National and International Publications in reputed Journals and international conference. He is guiding the Research Students in the area of Information and Communication Engineering at Different Universities. He is also editor and reviewer of various national and international Journals. He is contributing the academic and research experience in national and International Countries.
Dr. Jayabrabu Ramakrishnan obtained Ph.D Computer Science in 2013 from Bharathiar University, Coimbatore, Tamil Nadu, India. He has published many research articles in various international journals and conferences. His area of research includes Data Mining, Intelligent Agents and Information Systems.
Dr. Dinesh Mavaluru is currently working as Assistant Professor in the Department of Information technology at Saudi Electronic University, Saudi Arabia. He received a Ph.D. from B S Abdur Rahman University in 2014. His research interests span both data science and network science. Much of his work has been on improving the understanding, design, and performance of parallel and networked computer systems, mainly through the application of data mining, statistics, and performance evaluation. Committed to helping students identify and develop their own passions while becoming successful and confident scholars and learners. Exceptional track record of research success with multiple published articles in highly indexed journals and conferences.
Dr. Amira Elsir Tayfour has received her Doctorate from Sudan University for Science & Technology. Her research interest includes Image Processing, Machine Learning, Artificial Neural Networks, Network Security, Block Chain Technology, Networking, and Wireless networks. She is a head of Information System Department in King Khalid University Tomaha Branch. She has experience in computer maintenance. She is a member of various Academic committees. She is chairwoman of the Smart App Olympiad Arbitration Committee. She is guiding the Research Students in the area of Information System and Computer Science at King Khalid University Tomaha Branch. As expertise is less it continues in the various National and International Publications in reputed Journals and international conference.
Omer Elsier Tayfour obtained his M.Sc. degree in Computer Engineering & Networks from University of Gezira, Sudan. Ph.D. student at School of Electrical Engineering, Universit Teknologi Malaysia (UTM), Malaysia. He has 10 years of teaching experience in undergraduate level in the field of computer network & communication Engineering. His research interests include Software Defined Network, network virtualization, intrusion detection system, engineering project management.
Karzan Wakil is a lecturer and researcher in the Sulaimani polytechnic University, Iraq. He received his B.Sc. degree in Computer Science, College of Science Education from University of Salahaddin. Iraq, 2006, and his M.Sc. degree from the Department of Computer Science in the Faculty of Computing, University Technology Malaysia (UTM). Malaysia, 2013. Currently he is a Ph.D. student in the Department of Software Engineering, Faculty of Engineering, University Technology, Malaysia. He is working as a lecturer from 2006 till now, and at the same time, he has served as an ICT Director in University of Human Development. In 2016, he became the head of Science Department in the Institute of Training and Educational Development in Sulaimani, Iraq. His research interests are in Web Engineering, Internet of Things, Software Engineering, Web Development, Software Development, Web and Software Modeling, Artificial Intelligence, Information Retrieval and Educational Development.