Comparator trees for winner-take-all circuits
Section snippets
Background
Hardware implementations of Kohonen's self organising map (SOM) and the closely related learning vector quantisation (LVQ) algorithm [5] have received much attention in recent years [3], [11]. These algorithms have been shown to be of value in a variety of applications including signal processing. Where such an algorithm is applied in a real-time signal processing context a short and bounded response time is required, for example [14].
In the SOM algorithm a set of reference vectors (also
Comparator tree architectures
This section starts with a discussion of the specification required of the winner-take-all circuit. Following that specification is an overview of basic building blocks that may be used to construct a two-input comparator appropriate to later inclusion within the tree circuit.
Area and delay results
This section provides area and delay results for the architectures above. Three architectures are considered:
- (1)
A basic iterative architecture specified in synthesisable VHDL according to Eq. (6).
- (2)
An iterative architecture in which the g and l signals are propagated using look-ahead as in , .
- (3)
A multiplexor architecture as described in Section 2.4.
Conclusions
Three architecture styles have been investigated for the construction of multi-input comparator trees as applicable to the winner-take-all calculation in a digital implementation of a neural network. In the case of purely combinational logic architectures for a winner-take-all circuit it has been shown that the basic iterative architecture provides a compromise between area and performance. The look-ahead architecture provides the least logic delay but with the greatest area. For the same
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