Implementation of a CNN-based retinomorphic model on a high performance reconfigurable computer

Abstract

The complexity of hardware design methodologies represents a significant difficulty for non-hardware focused scientists working on accelerating the simulation of complex bio-inspired applications. An emerging generation of electronic system level (ESL) design tools is been developed, which allow software–hardware codesign and partitioning of complex algorithms from high level language (HLL) descriptions. These tools, together with high performance reconfigurable computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of highly parallelizable algorithms. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, are analyzed. A model for the first synapse of the retina, based on a discrete-time sequential CNN architecture suitable for FPGA implementation proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results showed that, with a minimum development time, a 10×acceleration, when compared to the software emulation, can be obtained.

Introduction

Bioengineering combines fundamental knowledge from medicine and biology with other more technological domains, such as electronics engineering, computing, optics, etc. In this context, the design of bio-inspired systems has been one of the research areas which has received more attention in recent decades. In particular, the development of retinomorphic models, could help understanding how the retina processes data, and support future research both in medicine and engineering applications. During last years, several retina models have been proposed. Some of them were based on OPL filters [1], others used a CNN-based approach [2]. Although some of them were thought to be implemented as electronic circuits, frequently this models were too complex for real-time execution, and were used just for simulation purposes. The main challenge to be addressed is the fact that biological systems are complex environments, dynamic and unpredictable, which depend on many unknowns difficult to uncover. Making realistic models of these systems is complex because it requires a deep and accurate knowledge of the real system, techniques to extract the relevant data and tools to solve highly complex calculations. Fortunately, the objective in many cases is not to obtain an ideal model of the biological system, but to imitate the way it processes data to develop more or less simple systems that reproduce a given phenomenon of interest.

Once an adequate model has been extracted, the following issue is to provide the high computing resources required, since very often even the simplest model would handle data quantities that exceed the current computer systems capacity. The use of approximation, simplification and linearization techniques can cope with the implementation, making it feasible, although they also introduce errors and uncertainties that cause the models to be less realistic and accurate.

Traditionally, computing systems used to emulate bio-inspired models have used software programs running on standard microprocessors. Despite of their flexibility and ease of development, the sequential nature of these computers restrict their performance when dealing with the massive-parallel systems that these bio-inspired models usually require. Moreover, increments of performance can only be achieved by increasing clock speed, which is limited by the microelectronic technology. The use of High Performance Computers (HPC), consisting of multiple processors and/or processing nodes, has helped to improve the performance of simulators by exploiting an application's coarse-grain parallelism while preserving the flexibility of conventional platforms. However, when the software approach cannot meet specifications, the use of specific hardware is an alternative that can further improve performance by exploiting fine grain parallelism, thus mimicking biological systems inherent parallelism.

During the last decade, the tendency of using reconfigurable hardware (FPGA) has taken an increasing interest. These devices improve precision and design flexibility, while simultaneously reducing cost and developing time with respect to ASICs due to the nature of the devices and development tools provided. With clock frequencies an order of magnitude lower than that of typical microprocessors, FPGAs can provide greater performance in application domains like real-time video or image processing algorithms as they take advantage of their fine-grained parallelism. This has also propitiated that FPGAs were commonly used as platforms for massive-parallel systems, such as CNN emulation and acceleration [3], [4], [5], [6]. However, the design process with these devices is not exempt of difficulties as traditional methodologies, based on hardware description languages (VHDL, Verilog, etc.) still require deep hardware skills from the designer.

Recently, a new generation of tools for highly complex circuit design is been developed. This new methodology, known as ESL (Electronic System Level), aims to target the problem of hardware–software co-design from system level, untimed descriptions, using different flavors of high level programming languages, such as C, C++ or matlab. Also, a new generation of hybrid supercomputers, called HPRCs (High Performance Reconfigurable Computers), is been developed to take full advantage of the new co-design tools. These HPRC systems provide the standard microprocessor nodes, plus new closely coupled reconfigurable nodes based on FPGA chips. Taking advantage of both coarse and fine grain parallelism, HPRCs are able to combine the benefits of hardware- and software-only implementations.

In this paper, an implementation of a model for the first synapse of the retina is proposed, which is based on a discrete sequential CNN architecture, on a HPRC platform from DRC Computers [7].

The rest of the paper is organized as follows. Section 2, summarizes some of the main ESL tools and their features, focusing in CoDeveloper ${}^{™}$ design flow, an ESL IDE from Impulse Accelerated Technologies, Inc. [8] that was used for hardware–software co-design. Section 3 depicts a hardware architecture for a CNN and the projection of the model of the first synapse of the retina under this paradigm. Section 4 describes the implementation of the retinomophic model on a HPRC. Section 5 analyzes the results and performance gains obtained. Section 6 summarizes some of the key remarks that have to be observed when using the new system level design methodologies, evaluates their suitability for the non-hardware specialist scientist, and provide some keys to get better results with this kind of tools according to our experience. Finally, main conclusions and future research is included in Section 7.