A compact spike-timing-dependent-plasticity circuit for floating gate weight implementation

doi:10.1016/j.neucom.2013.07.007

Neurocomputing

Volume 124, 26 January 2014, Pages 210-217

https://doi.org/10.1016/j.neucom.2013.07.007 Get rights and content

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Abstract

Spike timing dependent plasticity (STDP) forms the basis of learning within neural networks. STDP allows for the modification of synaptic weights based upon the relative timing of pre- and post-synaptic spikes. A compact circuit is presented which can implement STDP, including the critical plasticity window, to determine synaptic modification. A physical model to predict the time window for plasticity to occur is formulated and the effects of process variations on the window is analyzed. The STDP circuit is implemented using two dedicated circuit blocks, one for potentiation and one for depression where each block consists of 4 transistors and a polysilicon capacitor. SpectreS simulations of the back-annotated layout of the circuit and experimental results indicate that STDP with biologically plausible critical timing windows over the range from 10 µs to 100 ms can be implemented. Also a floating gate weight storage capability, with drive circuits, is presented and a detailed analysis correlating weights changes with charging time is given.

Keywords

Spike timing dependent plasticity

Neural networks

Floating gate

MOSFET

Cited by (0)

A.W. Smith received his MEng degree in Electrical Engineering & Electronic Engineering from the University of Liverpool in 2008. He is currently undertaking his PhD at the same institute since 2008, specialising in biologically plausible hardware for neural networks. Current research interests include hardware/software neural network implementations, semiconductor physics and floating gate devices.

L.J. McDaid graduated from the University of Liverpool UK with a B.Eng. (Hons) in Electrical and Electronics Engineering in 1985 and subsequently completed his PhD in Solid State Devices from the same institution.

He is currently employed as a Professor in the School of Computing and Intelligent Systems at the University of Ulster, N. Ireland. Dr. McDaid is currently guest editor for a special topic entitled “Biophysically based Computational Models of Astrocyte – Neuron Coupling and their Functional Significance” to appear in Frontiers in Neuroscience and he has co-authored over 100 publications in his career to-date.

Dr. McDaid is a founder member of the Nanoelectronics research group within the Intelligent Systems Research Centre (ISRC) at the Magee Campus of the University of Ulster. His main research interest is software/hardware implementations of neural based computational systems and he has several research grants in this domain. His ultimate vision is to understand and model the mechanisms that underpin self-repair in the human brain thus providing the blue print for advanced architectures that exhibit a fault tolerant capability well beyond existing computational systems.

S. Hall (FIET, CEng, SMIEEE) has interests spanning materials characterisation, device physics and innovative device design and gate level circuits. He has over 200 conference and journal papers, mainly in the area of silicon technology, devices and circuits. These include novel measurements and contributions to the understanding of MOS related interfaces and materials quality. He has successfully designed and built novel MOS and bipolar devices in silicon for over 20 years. More recently, his work encompasses hi-k dielectrics, novel devices and gate level circuits relating to micro-power and biologically inspired concepts. He was Technical Programme Chair of ESSDERC 2008, and currently sits on the Steering Committee of ESSDERC/ESSCIRC and INFOS, for which he was vice-Chair in 2009 and a member of the Steering Committee from 2009. He was Head of Department of Electrical Engineering & Electronics at the University of Liverpool, UK from 2001 to 2009.