OpenFPGA CoreLib core library interoperability effort

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Abstract

This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.

Introduction

Field Programmable Gate Arrays (FPGAs) are increasingly used to perform application-specific, hardware-accelerated computations. By customizing the data path, memory, and computing elements, FPGA circuits can be made to perform application-specific computations much more efficiently than traditional programmable processors. Many commercial applications, in a wide variety of domains, have been successfully implemented using FPGAs for performance-critical processing. These applications have included video processing, data communications, scientific and financial computing, and many others. The accelerated portions of these applications are typically characterized by the use of massive parallelism at the circuit level. Recent advances in FPGA architectures, as well as advances in FPGA-based computing platforms and related tools, have played strong roles in the increased use of FPGAs for such applications.

Most FPGA designs used for application-specific computation are created using hardware description languages (HDLs) such as VHDL and Verilog. The HDL-based design methodology, however, provides a relatively low level of abstraction when compared to traditional programming languages. The HDL level of abstraction requires that the application programmer have a solid understanding of fundamental digital design techniques as well as knowledge of the underlying FPGA architecture. The use of HDLs for designing application-specific accelerators is very time consuming and limits the use of FPGAs to those with specialized digital design skills.

In order to provide higher levels of abstraction and improve the ease of programming the FPGAs, a number of high level languages (HLL) and related compilers have emerged. These higher level FPGA programming tools allow a programmer to create a circuit within an FPGA from a high-level specification such as C. This provides increased productivity, shorter development times and greater ease of use to FPGA application designers. While there may be a performance, power or size penalty associated with using such tools, an increasing number of application developers are finding them to be productive and capable additions to their existing FPGA development environments.

HLL programmers obtain the best results by combining use of high-level tools with traditional HDL. Hardware description languages are used to describe high-performance circuits at a relatively low level of abstraction. Designers prefer to reuse such circuits because of their high performance and the high-cost of developing these cores from scratch. High-performance circuits that are designed in a way to facilitate reuse are often called Intellectual Property cores or IP cores for short. In such a hybrid approach to FPGA design, certain critical components may be hand-crafted using HDLs, while other parts of the system are either described at a high level using an HLL compiler, or assembled using off-the-shelf IP cores.

This hybrid approach to FPGA design is similar to practices common in software development. A common practice during software development is to use architecture-specific or platform-specific libraries, with the goal of increasing performance and reducing development time. For example, software programmer targeting such widely divergent platforms as DSPs (in an embedded system) or the Linux operating system running on a Pentium-class processor may be using the same programming language (be it C, C++ or some other language), but will almost certainly be using libraries and application programming interfaces (APIs) that are unique to that target, or unique to their specific type of application. In extreme cases, such as in DSP applications, the software programmer may be required to drop into assembly language in order to achieve a required level of performance.

While this approach of mixing high-level target independent code with low-level application-specific cores is effective, there are currently no accepted standards that address the integration of IP cores into high-level programming languages. In the absence of standards, the IP providers, tool vendors and application developers must spend extra time and effort to port and integrate existing or new IP cores into HLL tool environments. Further, the approach for integrating IP cores into HLL tools varies from vendor to vendor. The lack of a standard has limited the growth and adoption of HLLs in FPGA-based computing. A standard is needed to simplify the process of integrating IP within higher-level design tools. This paper will summarize the efforts of the OpenFPGA[1] CoreLib working group to identify and create such a standard.

Section snippets

Project goals

The overall goal of this effort is to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. The specific goals of this effort include the following:

  • Develop a standard for describing the interface and operating characteristics for cores facilitating the integration of cores within high-level programming language compilers and other FPGA design tools.

  • Develop a standard for libraries of

Related IP reuse efforts

There have been many efforts to improve design productivity by facilitating the reuse of circuit cores. These efforts, targeted primarily to the design of ASICs, simplify the process of reusing and integrating existing circuit IP within a complex ASIC design. The OpenFPGA CoreLib group will reuse existing concepts and infrastructure to support the goals of the effort. This section will summarize and contrast several of these efforts with the goals of this project.

opencores.org [2]: This effort

Importing IP within current HLL compiler and tools

A number of compilers and tools are emerging to generate FPGA circuits from programs written in a high-level language. These tools vary in their approaches to integrating IP cores into their environment. Just as there is an effort to study existing IP reuse efforts, there is also an effort to study the various approaches used by HLL tools to integrate user IP cores. This section summarizes the approaches used by several tools to integrate IP cores.

Proposed IP interface approach

A major challenge facing this effort is to define a standard that allows complex IP cores to be easily used and instantiated within a high-level specification. At the same time, this standard should be expressive enough to describe all of the technical details of the IP core that are necessary for interfacing the core to the other circuits synthesized from the high-level code. This task requires the careful representation of many details associated with a given circuit library while abstracting

Core library standard

In addition to a standard for describing reusable circuit IP cores, this effort is developing a standard for packaging these cores into reusable libraries. The goal of this library effort is to facilitate the collection and distribution of cores to a large population of application developers. Fig. 1 demonstrates this concept. A variety of libraries are created that meet an accepted standard. These libraries are made by independent vendors for a variety of purposes and applications. At the same

XML-based standard

The approach we are currently pursuing is to create an extensible markup language (XML) specification for representing the details necessary for describing cores and libraries. Further, we are basing this specification on the Spirit Consortium IP-XACT format. This section will summarize our proposed approach for building upon the XML-based IP-XACT specification to represent FPGA core libraries.

There are many data objects and views associated with any given circuit library. These views include

Example

Floating point IP core implementations can vary in their optimizations strategies and resource utilization. [24], [25], [26], [27], [28]. Two IP core examples are presented in this section to demonstrate the need for a standard that allows seamless interface between IP cores and high-level languages. The first example is a simple square root and the second is CORDIC (Coordinate Rotation Digital Computer) [28]. Both examples involve the seemingly simple square root function but demonstrate how

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