Modelling and experimental verification of the effect of parasitic elements on the performance of an active-clamped current-fed DC–DC converter

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Abstract

Current-fed DC–DC converter has received a lot of attention recently for the fuel cell power source applications. This is due to its attractive features, such as low input current ripple, high voltage conversion ratio and high efficiency. Unfortunately, a high voltage stress across the switches and hard switching is the main drawback of the current-fed topologies. Therefore, an active clamp circuit is often implemented to suppress any voltage overshoot across the switches and achieving zero-voltage switching. In this paper, based on detailed analysis on the converter performance it was found that parasitic elements of the converter can have a large impact on promising features of current-fed converters with an active clamp. This has not been reported in the literature. It has been shown through an in-depth analysis on the converter that particularly during the switch overlap period the parasitic elements create undesirable oscillations leading to additional circulating energy that adds to the conduction losses of the converter. It also results in voltage ringing across the clamp switch, oscillations in the current through the clamp circuit and high voltages across the bridge switches, even when the switches are conducting. Based on this finding a number of modifications have been proposed and these have been verified by thorough simulation and experiment.

Introduction

For the future generation of clean electricity, hydrogen fuel cells rank as one of the dominant technologies. There are a several types of hydrogen fuel cells, categorised by the type of electrolyte. One of the most popular types of fuel cell (FC) for low temperature application (below or around 200 °C) that uses hydrogen as a fuel is the proton exchange membrane fuel cell (PEMFC) [1], [2]. The PEMFC can be used for stationary as well as automotive power generation. The output power characteristics of the PEMFC are determined by the kinetics of the electrochemical reactions, internal electrical and ionic resistance and the crossover of reactants. Due to the ohmic losses the output voltage of the PEMFC is not constant but reduces with power demand, as shown in Fig. 1. In most stationary and automotive applications, the low output voltage must be stepped up to the required DC link voltage level. In addition, the FC is sensitive to the ripple current which decreases the service life of the stack and impacts on the diffusion layer of the FC stack [3]. The selection of the DC–DC converter topology for FC power conversion systems requires dealing with FC source specifications, such as low voltage and high current whilst maintaining low input current ripple, high voltage conversion ratio, and high efficiency. A number of different DC–DC converter topologies have been proposed for this application [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. Among those, the isolated current-fed DC–DC converter (CFC) with high frequency transformer, as shown in Fig. 2, has shown to be the best solution in achieving most of the properties required for the FC generator system [16]. However, one of the CFC drawbacks that is the voltage stress across the switching devices from hard-switching operation which also results in reduced converter efficiency. Additional circuitry must be added to limit this. The current-fed converter with active clamp circuit has promising features over other topologies for reducing the voltage stress across the converter switches which allows the usage of a smaller and more efficient switching device with lower voltage rating and achieves zero-voltage switching ZVS [16], [17].

There is a large body of literature [9], [11], [13], [18], [19], [20] that has proposed different CFC topologies in combination with active clamp circuit. All the researches have been restricted to describe the circuit configurations and steady-state modelling. However, the impact of the parasitic elements on the performance of the active clamp CFC are typically not shown in the literature because they are either implemented with low-power low-DC link voltage specifications [11], [12] or that significant effect is ignored. In this regard, to accurately assess the converter performance, in-depth modelling analysis of an active clamp CFC with the parasitic elements is developed in this paper. It was found that the most significant parasitic elements that have the biggest impact on the converter performance include the stray inductances of the switching devices, the stray capacitances of the boost inductor and transformer, and the parasitic capacitance of the rectifier diodes. It has been noted that these elements create undesirable oscillations leading to additional circulating energy which adds to the conduction losses of the converter. It also results in voltage ringing across the clamp switch, oscillations in the current through the clamp circuit and high voltages across the bridge switches, even when the switches are conducting and EMI radiated noise through the converter.

Modification approaches to eliminate or reduce such effects have been developed and implemented in a prototype converter. Simulation and practical results show that the active-clamped CFC can maintain high efficiency for the entire load range with these developed modifications. Waveforms of a 1.2 kW prototype system are presented and compared with results of thorough simulations.

Section snippets

Detailed analysis of the effect of parasitic elements

This section shows a brief description of the operation of the CFC system. The proposed analysis has been applied and implemented on active-clamped CFC with voltage doubler configuration [16], as shown in Fig. 3. The timing signals and waveforms of various voltages and currents for the circuit in Fig. 3 are shown in Fig. 4.

During the overlap period (d1Ts/2 and/or d2Ts/2) all bridge switches conduct and the bridge voltage is zero. When one pair of diagonal bridge switches is turned off, the

Validation of analysis

To validate the previous theoretical analyses, parasitic elements were included in the PSpice model as described in Section 3.1 below. After this, the PSpice model has been verified by experimental results as described in Section 3.2.

The parameters and components that have been used for the simulation and measured results are given in Table 1.

Remedies to overcome effects of parasitic elements

This section introduces a number of modification approaches that have been taken in the design of the converter in order to minimize the parasitic elements effect and further improve the converter’s efficiency,

Validation of the simulation model with the developed modifications

The objectives of this section are:

  • Evaluate the converter performance with the modifications developed in Section 4.

  • Show current and voltage waveforms of the converter with all the modifications implemented to prove that they have the desired effect.

  • Compare the measured results with a limited number of waveforms obtained from a PSpice model that includes the modifications, in order to validate the PSpice model.

Fig. 19a and b show the measured waveforms of the current through the clamp circuit i

Selection of the dead time

To ensure ZVS of the bridge switches at the turn-on, the required dead time Tdead1 between the bridge switches and the clamp switch Sc should not exceed the full resonance period between Cp3Cp4, Cpc and Lσ (see Fig. 4)Tdead1=2π(Cp3+Cp4+Cpc)Lσwith Cp3 = Cp4 = 16 nF (These values are obtained from the datasheet of SKM120B020 MOSFET device), Cpc = 10 nF (This value is obtained from the datasheet of IXFN73N30MOSFET device) and Lσ = 2 μH, this yields Tdead1  1.8 μsec.

It was observed through simulation and

Conclusion

Based on the detailed modelling and hardware implementation of an active-clamped current-fed DC–DC converter, it has been observed that during the overlap period the parasitic elements create undesirable oscillations in the voltage and current through converter which can be categorised as follows:

  • Voltage ringing across the clamp switch and oscillating in the current via the clamp circuit are occurred whenever the clamp current reached zero.

  • Voltage ringing across the bridge whenever the voltage

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