Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory

Highlights

• Experiments show fewer disturbed cells, leading to fewer extra write/read operations.

• Our technique improves performance by 47% over the state-of-the-art.

• Performance and endurance are improved by 47% and 42%, respectively.

• Operational energy is reduced by 36% with only a ∼1% increase in embodied energy.

• Embodied energy can be offset within 4 days or take 4 years depending on scenario.

• For most workloads, the increased lifetime alone recoups the embodied energy.

Abstract

While Phase Change Memory (PCM) is gaining popularity in next generation systems compared to conventional DRAM and Flash, write disturbance due to crosstalk remains a significant challenge to PCM performance and reliability. To address this concern we propose a multi-tiered compression (MTC) technique combined with novel encoding that can decrease the probability of write disturbance. MTC compresses a high proportion (>94%) of cachelines by a small predictable amount (e.g., 40- or 56-bits of a 512-bit block) while maintaining data similarity vital for optimizing PCM writes. By detecting data patterns prone to crosstalk, we use encoding, correction pointers, and a hybrid approach to reduce the instances of write disturbance. We use MTC reclaimed bits to store the encoding. Thus, our approach requires only five additional auxiliary bits per 512-bit cacheline, minimizing the embodied energy (fabrication) overhead to mitigate write disturbance. Additionally, through a multi-objective optimization, dramatic endurance improvements are possible while maintaining nearly all write disturbance improvement.

Our technique improves performance, endurance and write energy by 47%, 42% and 36% versus the state-of-the-art with nominal (circa 1%) increases to embodied energy. When considering the full life-cycle impact, the additional area of our MTC with encoding approach is mitigated by the use-phase benefits within 60 days for a high performance system and in less than four years of use for a desktop system. In nearly all studied scenarios, the improved lifetime provided by our MTC and encoding approach easily recoups the required additional upfront manufacturing energy.

Introduction

New memory technologies continue to emerge with promises of improved density, non-volatility, energy efficiency benefits, and increases in performance. Of course each new technology also comes with unique challenges which must be addressed to reach their full potential. Phase Change Memory (PCM) is likely the most mature of these technologies and is receiving considerable attention as a useful element in tiered memory solutions. Compared to DRAM, PCM has a competitive access latency, with performance overheads of only around 20%. However, there are considerable advantages in density [1] and of static energy. PCM has been recently commercialized by Micron and Intel in a “3D Xpoint” memory with the commercial name of Optane Persistent Memory.

Like many of its emerging memory competitors, PCM still faces a number of challenges that limit its viability for large scale Flash and/or DRAM replacement. Recent studies show that scaling PCM to technologies below 20 nm significantly reduces the reliability of memory cells [2] due to impacts from crosstalk. Scaling compacts more cells into the same die area and contracts the spacing between bitlines and wordlines. When the cells are placed in closer proximity, the heat for changing the state of a cell can impact neighboring cells both along the same wordline or between adjacent wordlines. This phenomenon, referred to as write disturbance [2], is amplified by this scaling. While write disturbance can be mitigated by repeated writing attempts, this creates several problematic behaviors. For each memory write, write disturbance errors within the wordline must be corrected immediately by rewriting disturbed cells, requiring additional read and rewrite operations. Furthermore, rewritten cells themselves may cause additional write disturbance, leading to many write-read iterations during a single memory write operation. While this is undesirable for correcting bits within the same word, bits may be affected in other words from neighboring bitlines, which can require considerable additional reads/writes and subsequent performance delays and energy overheads.

Several techniques have been proposed to minimize disturbance due to crosstalk. One type of crosstalk is crosstalk between bits activated in the selected wordline. We refer to this as wordline crosstalk. DIN attempts to reduce wordline crosstalk through compression and encoding [2]. Another form of crosstalk is crosstalk in the neighboring memory rows of the active wordline. We refer to this as bitline crosstalk. Authors in [3] use extra storage dedicated for fault tolerance to store disturbed data in the neighboring rows. ADAM [4] attempts to address both bitline and wordline crosstalk through interleaving data in adjacent rows with dummy data to avoid useful data from being disturbed. Unfortunately, these previously proposed techniques typically require either significant compression or the introduction of additional fault tolerance bits to be effective.

One way to address this concern is to reclaim space for this encoding using a lightweight compression that is effective at reclaiming a small amount of space in a high percentage of cases and to develop a fault tolerance technique that minimizes the necessary reclaimed space to to store encoding bits and be effective. The alternative is to add additional storage for fault tolerance which increases costs, increases environmental impacts, and reduces overall sustainability [5]. Prior work, such as WLCRC [6], shows that for a wide range of typical workloads, only 30% of cacheline writes to memory can be compressed using lightweight compression approaches such as ADAM. Thus, a technique requiring compression to mitigate bitline and wordline crosstalk would be ineffective for more than 70% of the data blocks written into memory for typical applications. WLCRC takes a first step toward more effective compression coverage such that it achieves a small compression ratio but can be applied to 90% of memory blocks written to memory. In this paper, we propose a multi-tiered compression (MTC) technique that compresses more than 94% of memory writes. MTC reclaims at least as many bits as WLCRC (40 bits) and often may reclaim 40% more space (56 bits) without introducing extra complexity while achieving this better compression coverage. Additionally, MTC retains data similarity between accesses which ensures techniques such as differential write remain effective. We explore two approaches to utilize the reclaimed bits of MTC to mitigate write disturbance. First, we use a word-level encoding that reduces the number of aggressor cells that lead to write disturbance of neighboring victim cells. Second, using pointers we track the locations of the most impactful aggressor cells, i.e., aggressor cells with the largest number of neighboring victim cells. Aggressors with the highest disturbance probability are inverted to avoid changing their cell. A pointer is used to indicate which locations were inverted for disturbance mitigation in order to recover the original value. Additionally, we propose a hybrid approach that utilizes both encoding and pointers to minimize both wordline and bitline write disturbance.

In particular, this paper makes the following contributions:

• We characterize realistic workloads and use them to stress our multi-tiered compression technique and examine its suitability to reduce write disturbance in deeply-scaled PCM.

• We propose a new data encoding with a cost function that is tuned to reduce both bitline and wordline write disturbance.

• We propose a hybrid encoding with pointers technique that best filters out aggressor cells that disturb potential victim cells.

• We discuss the holistic sustainability of a hybrid approach to write disturbance mitigation for techniques that introduce additional storage for fault tolerance.

• We provide additional cost function optimization studies, which further enhance the effectiveness of the multi-tiered compression technique.

The remainder of the paper is organized as follows: Section 2 provides relevant background and related work for memory semiconductor sustainability, PCM, and write disturbance. Section 3 introduces the experimental settings used in our evaluation. We describe and characterize MTC for representative workloads in Section 4 and then present applying coset encoding and pointers for write disturbance minimization in Section 5. Section 6 introduces our combined compression with encoding approach. A multi-objective approach for minimizing energy and improving endurance is related in Section 7. Section 8 evaluates the efficiency of our approach against the state-of-the-art approaches. Finally, we conclude the paper in Section 9.