Optimal soft error mitigation in wireless communication using approximate logic circuits
Introduction
The recent proliferated growth in ubiquitous sensor and wireless communication technologies and applications has tremendously increased the demands for sustainable resource methods for efficient Soft-Error (SE) mitigation in smart computing. Due to a large number of error occurrences in digital circuit frameworks, there have been ecosystem concerns as energy consumption and carbon dioxide emission have increased globally [1]. Furthermore, the digital circuit failure poses a slow growth of technology scaling. Most circuits mass-produced on cutting-edge technologies are more susceptible to errors because of the attenuation in the dimensions of a transistor and the growth in the total gates in a chip. Moreover, advanced transistors effects, like negative-bias temperature irregularity, add up to erratic gate failures for the period of the chip lifetime. Also supply voltage differences, manufacturing differences, and temperature differences in digital circuits pose a challenge to reliability [2].
An approximate computing technique has been introduced in logic circuits to improve computational overheads. Therefore, approximate logic circuits give a generalized framework in optimizing SE mitigation caused by permanent, temporal, and intermittent failures. Its performance is much connected to logic function as compared to the original circuit. But it functions differently from the original circuit, the approximate logic circuits efficiently detect and correct SEs whenever its intersections with the original circuits. More significantly, the approximate logic circuits can be applied in triple modular redundancy (TMR) [3], [4] as an alternative for precise duplicates of the master copy and the manufacturer chooses the approximation level. A closer approximation offers better fault tolerance but extends the area and power. On the other hand, such constant adjustment is not promising when precise TMR is applied. However, the major challenge is how to generate an optimal redundant logic circuit capable of masking high probability faults while reducing the area and power overheads.
Fault-tolerant methods are characteristically grouped into time, information, and hardware redundancy methods [5]. Amid hardware redundancy methods, a recognized masking scheme, TMR is employed in critical applications. It is applied at different points of concept from system-level to transistor side, to improve protection against temporary and permanent errors. Information redundancy methods, for instance, the codes of error detection and correction (EDAC), are more efficient either for dual or singular errors. As a consequence, these codes of EDAC are usually useful to communication and cognitive protocols, though unrealistic in general cases due to an unguaranteed low array of errors. Finally, the time redundancy method is fundamentally weak to permanent failures to cause severe performance drawbacks. The TMR is capable of mitigating both temporary and permanent errors to handle the variation of probable error mechanisms to occur in advanced technologies. On the other hand, TMR undergoes steep overhead in regards to energy consumption and area recovery.
Inspired by the above-mentioned studies, this paper examines SE mitigation and proposes an energy-efficient probability-based method that considerably improves soft error mitigation.
The key contributions are summarized as follows:
- 1.
develop a framework for generating approximate logic circuits by performing efficient iterative logic modifications to minimize the error coverage area.
- 2.
propose an energy-efficient algorithm based on probability approximation to improve SE mitigation in the wireless communication networks
- 3.
using some extensive numerical analysis, the study confirms the effectiveness and robustness of the proposed algorithm and its superiority as compared to other existing SE mitigation algorithms.
The remaining parts of this work are structured as follows. In Section 2, several related pieces of literature are reviewed and summarized. A logic-based approximation technique is examined in Section 3, while the design technique of the ALC system is presented in Section 4. In Section 5, the proposed technique and algorithm is illustrated. Simulations and numerical analysis are provided in Section 6. Finally, the conclusion is presented in Section 7.
Section snippets
Related work
In recent times, minimizing energy consumption in digital logic designs has received considerable attention. Thus, the adjustable digital logic circuit has received substantial consideration due to its capacity of ensuring minimized energy usage in circuits. The work of [6], utilized Plessey Logic Block which is an essential unit of Field-Programmable Gate Array (FPGA) to develop an adjustable ideal parameter. In the experiments, the design of the separate logic fragments is mainly enhanced for
A logic-based approximation technique
In this section, we examine an approximate logic circuit by applying probability to mitigate the errors. A dynamic SE mitigation technique is proposed, where an ALCs are generated from the primal circuit by performing efficient iterative logic modifications. These iterated modifications do not preserve the primal functions of the logic, rather, streamlines it by deviating from its conventional characteristic to reduce the error coverage. Two major constraints characterize the approximation
A line-based approximation technique
Assuming a fixed error in one of the lines has a low capacity to be tested implies that only a few input vectors can be used in testing the error. Therefore, a quality approximate circuit may be designed if a constant value is assigned to a line. This modification is hereby referred to as line approximation [23], [24]. In this case, the probability of error related to this modification is comparative to that of the input entities that experiment with the fixed error. Alternatively, the area
Proposed technique
In this section, we examine the proposed energy-efficient probability-based approximation technique [19] to mitigate soft errors. Initially, we assume that the true device correctly detects the soft error (SE) signal; we can identify the true location using probability-based approximation expressed as in Eq. (3).where means the probability that SE is correctly detected and reaches the desired area; is the probability of SE acknowledged correctly by a device in the vulnerable
Performance evaluation
In this section, we implemented the experiments of our proposed technique on C++ using the CUDD package. The demonstrations of the CUDD is based on the LGSynth93 public domain benchmarks. Using a GHz Intel Corei5 computer with GB of memory on a Windows Operating System, we implemented our simulations. The evaluation of our experiment is to show the performance of the proposed technique by simulation. We assume that the sensor nodes of the communicating devices are deployed randomly at
Conclusion
In this study, the soft error rate and other mitigation techniques were examined thoroughly. We proposed an energy-efficient probability-based approximation technique to mitigate soft error occurrence in devices. Simulations were performed to evaluate the proposed technique. The implications of the results were that the proposed technique moderately consumes less energy in soft error sensing and detection when directly compared with BICST and ROWR techniques. Also, the proposed technique
Authors’ contribution
Joseph Henry Anajemba: Conceptualization, Data curation, Roles/Writing – original draft; James Adu Ansere: Roles/Writing – original draft; Frederick Sam: Formal analysis, Roles/Writing – original draft; Celestine Iwendi: Funding acquisition, Investigation; Gautam Srivastava: Formal analysis, Roles/Writing – original draft.
Declaration of Competing Interest
The authors report no declarations of interest.
References (27)
- et al.
Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array
Sustainable Comput. Inform. Syst.
(2017) - et al.
Constant modulus algorithms via low-rank approximation
Signal Process.
(2019) - et al.
Survey of soft error mitigation techniques applied to LEON3 soft processors on SRAM-based FPGAs
IEEE Access
(2020) - et al.
Criticality aware soft error mitigation in the configuration memory of SRAM based FPGA
2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
(2019) Design and Analysis of Fault Tolerant Digital Systems
(1988)Mitigation of soft error rate using design, process and material improvements
2019 IEEE International Integrated Reliability Workshop (IIRW)
(2019)- et al.
Analyzing Impacts of SRAM FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
IEICE Trans. Electron.
(2019) Mitigation of soft error rate using design, process and material improvements
2019 IEEE International Integrated Reliability Workshop (IIRW)
(2019)- et al.
Runtime techniques to mitigate soft errors in Network-on-Chip (NoC) Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3
(2018) - et al.
Designing and evaluating redundancy-based soft-error masking on a continuum of energy versus robustness
IEEE Trans. Sustainable Comput.
(2018)
Advanced ECC solution for automotive SoCs
International Symposium on On-Line Testing and Robust System Design
Soft error and its countermeasures in terrestrial environment
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment
Sustainable Comput. Inform. Syst.
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