A novel FPGA local interconnect test scheme and automatic TC derivation/generation

Abstract

This paper presents a novel local interconnect testing scheme for field programmable gate arrays (FPGAs). To maximize parallel testing, error-detecting code is used for testing one portion of interconnects and functional test of D latch for another in a test configuration (TC). A polynomial run time algorithm is introduced for deriving a minimal set of TCs. An in-house CAD tool is developed to automate the generation of device configurations from the set of TCs.

Introduction

Field programmable gate arrays (FPGAs) are increasingly used to implement logic functions that traditionally have been designed into application specific integrated circuit (ASIC) technologies. State-of-the-art FPGAs have reached unprecedented levels of complexity, containing millions of equivalent logic gates, high speed I/Os, and embedded microprocessors and random access memory (RAM) blocks. Highly integrated system-on-a-chip (SoC) designs now contain tens of embedded components, such as FPGAs and intellectual property (IP) cores. Such systems present great challenges to test professionals. Existing testing methodologies require significant enhancement. New test methods that support low-cost test development and high reliability solutions are in great demand. This paper addresses testing and test development issues of FPGAs.

An FPGA is comprised of an n×n array of configurable logic block (CLB) and interconnect resources. Local interconnects are associated with CLBs, including I/O pins of CLBs, wire segments and programmable switches (PSs) that bring signals into and out of CLBs. Wire segments and PSs in global interconnects form horizontal and vertical routing channels that connect signals between CLBs. In Xilinx FPGAs most of the programmability is concentrated in local interconnect resources. A complicating factor is that the integrity of local interconnects cannot be verified without accessing CLB logic. This paper extends the work by the same authors on testing global interconnects in [1] to verify the integrity of local interconnect resources.

Prior work on interconnect testing can be found in [1], [2], [3], [4], [5], [6], [13], [14], [15], [16], [17], [18], where component testing assumes direct I/O access to a device and the use of an external tester while built-in self-test (BIST) typically utilizes the JTAG port of a device and requires minimum control from the outside. In [2], [3], [4], [6], problems of component testing for interconnects are considered, where [2], [3], [4], [6], [13], [14], [17], [18] focus on global, local, and global and local interconnects respectively. In [4], global interconnects are programmed to form “global busses” and are tested using classical bus testing vectors externally applied to the device. Testing for local interconnects can only be performed by passing test signals through the CLBs. In [3], [6], n one-dimensional CLB arrays, each containing n CLBs, are used for an n×n FPGA. Multiple fault detection is not guaranteed in [6] due to the use of XOR trees and D flip-flop (DFF) chains to propagate the test outputs.

The first BIST proposal for testing interconnect resources is a comparison-based approach by Stroud et al. [5]. They configure a subset of wire segments and PSs to form two groups of wires under test (WUTs). The two WUTs receive identical test patterns from a group of CLBs configured as test pattern generators (TPGs), and are compared by a group of CLBs configured as an output response analyzer (ORA). This approach has good fault coverage for shorts/opens on wire segments and stuck-on/off faults in PSs. However, the ORAs fail to detect multiple faults that have identical faulty behavior in the two WUTs groups. In [1], a parity-based error control coding technique is proposed for global interconnect testing. It supports superior multi-fault coverage. This paper extends the work by the authors on global interconnect testing in [1] to test local interconnects. The global interconnect and switch matrices are homogeneous and the local interconnect and PSs are irregular. This makes it more challenging to configure the local interconnect into the proposed conceptual bus structure used in the global and local interconnect testing. An extra complicating factor is that the integrity of local interconnects cannot be verified without accessing CLB logic.

The main objective of this research is to develop a low cost and efficient test for FPGA local interconnect in component test and/or BIST applications. This paper addresses three inter-related issues on local interconnect testing: (a) the development of a novel test scheme for local interconnects; (b) the investigation of a computerized algorithm for deriving local interconnect TCs. We model local interconnects and their test requirements using adjacency graphs, study the characteristics of these graphs, and present a polynomial run time algorithm that derives a minimal set of TCs, each defining a subset of PSs under test in a basic tile [19]; (c) the development of an in-house computer-aided design tool, TCcompile, to automate the generation of device configurations (DCs). TCcompile takes in a set of TCs obtained in step (b) for a basic tile, makes use of the physical device information of the FPGA, and automatically generates a set of DCs to be used to program the physical device.

The proposed testing scheme supports both BIST and component test. The TC derivation and DC generation methods are applicable to FPGAs of various architectures and sizes. This paper is organized as follows. Section 2 gives the background preparation. Section 3 presents the proposed testing scheme and gives the proofs for fault detectability. Section 4 introduces the FPGA interconnect model and the algorithm for deriving minimal TCs, and reports on the experimental results. Section 5 discuses the automated DC development environment.