A parallel algorithm for constructing reduced visibility graph and its FPGA implementation
Introduction
Geometric structures for environment representation play an important role in applications such as robotic path planning, hidden line elimination in graphics, and computer animation. One structure that has been of tremendous interest in the context of reachability studies, collision avoidance, shortest paths calculation etc. for robots is the visibility graph [1].
Visibility graphs in applications cited are typically defined in terms of intersection: Two points a and b are (mutually) visible if the line segment ab does not intersect any “forbidden” curve (a curve could be another segment in the plane, an edge of a polygonal/polyhedral object etc.). One of the early structures used in planning collision-free paths in robotics is the complete visibility graph [2]: Given an environment with a start point S, a goal position G and several polygonal obstacles with a total of V vertices, the complete graph has as its nodes the set N given by V∪{S,G} and as its arcs the set of all links (ni,nj) such that a straight line connecting the ith element of N to the jth element does not overlap any obstacle.
While the complete graph is of interest in some applications, some variants require less storage, are often easier to compute and adequate for robotics applications. One example is the reduced visibility graph defined in [1] and this is the subject of this paper. The reduced visibility graph is defined in terms of supporting segments. It turns out that given a pair of convex polygonal objects A and B, there are at most four distinct supporting segments. These four segments (along with the edges of the polygons) are adequate for calculation of Euclidean shortest paths in the plane with convex polygonal obstacles that is of direct interest in mobile robot path planning.
The work presented here applies to convex objects. Non-convex objects can be handled as the union of convex parts and further, the convex class has been established to be adequate for handling navigation of mobile robots [3]. Convexity has interesting consequences in terms of the algorithms developed.
Prior work on visibility graph construction has focussed on sequential algorithms [1]. A direct algorithm to construct the complete visibility graph of an planar polygonal environment with n nodes takes O(n3) time [2]. A simple sequential algorithm to compute the reduced visibility graph would also take quadratic time or more. Several algorithmic studies exist for planar and polyhedral environments taking into account also the degrees of freedom involved for the robots of interest. The ones that are directly related to the work presented here are [2], [3]. Work on variants of the visibility graph and their applications in the robotics area includes [4], [5]. Work on using the visibility graph and its characteristics for solving problems other than those relating to path finding also exist in the domain of computational geometry. One example is the algorithm of Dobkin et al. [6] for finding the largest empty convex r-gon in a simple n-gon P where the vertices of the convex r-gon correspond to the vertices of P. The authors in [6] describe an O(mn) time algorithm where m is the number of edges in the visibility graph.
There are many situations that benefit from construction of the visibility graph on the fly. These include an autonomous vehicle moving in a partially known environment. Another is a situation involving humans (with some disability) moving in (busy) public places carrying a computing gadget that is a source of information around them. There is a need for approaches to process the environment as fast as possible so that an appropriate response can be generated.
Another scenario motivating the design of special methods for high speed construction of visibility graphs is provided by Doyle and Jones [7]. The authors in [7] present a path planning strategy for a robot manipulator in high dimensional configuration spaces that constructs tangents (which are part of the visibility graph) during the search (for path) process. Heuristics are applied to construct a limited set of tangents from a point v to a two-dimensional obstacle plane defined by v, the obstacle centroid and the destination point. The tangents are computed by considering the set of lines from point v to the cross-section of the obstacle, which intersects the plane. The two lines with the greatest angle between them constitute the required tangents. The authors suggest optimal results can be obtained by defining more planes rotated along the line from the current position to the goal. The bottleneck, however, is in obtaining them in reasonable time in a sequential implementation. Custom hardware to accelerate the computations seems desirable.
In general, path planning methods in robotics that are fast in practice are often heuristic in nature. Heuristic methods may, however, fail to find a path sometimes even if one exists. On the other hand, exact algorithms are guaranteed to find a solution if one exists but have been slow when implemented on general-purpose PCs. Parallel solutions with a cost-effective approach are desirable. Those based on FPGAs provide this alternative. We elaborate on this below.
Advances in VLSI technology and availability of Electronic Design Automation tools have made the development of reusable, low-cost and high speed special purpose hardware possible. Recent research [8], [9] indicates that reprogrammable solutions such as ones using FPGAs offer a significant performance improvement over their microprocessor counterparts for many applications while keeping costs low. Studies indicate unprecedented levels of performance of current FPGAs at low power, mass and volume [8], [9].
Prior work on design of hardware-directed methods for environment representation includes the definition and analysis of a virtual rectangle for path planning [10] and a city-block metric-based discrete Voronoi diagram study [11]. The authors in [10] study in particular the construction of a visibility matrix for path calculations. To the best of our knowledge, there is no parallel algorithm or hardware implementation for the construction of the reduced visibility graph.
While the graph is a central tool in exact approaches to path planning, development of a high speed solution with low area requirement poses difficulties. A novel aspect of our approach is incorporation of parallelism at the algorithm level along with careful use (and reuse) of hardware to achieve the parallelism in the implementation. Our algorithm minimizes use of sophisticated data structures and accomplishes the construction of the graph by (a) assigning binary codes to the vertices of the objects and (b) formulating the construction in terms of answers to “Is a point p above a line L?” type of queries. The latter is realized in hardware through simple elements avoiding division or other expensive operations. Our FPGA implementation is based on reuse of hardware allocated for the earlier phase of the algorithm in the latter phase thereby realising high speed construction of the graph for a fairly large environment (with considerable nodes) in a single chip.
The contributions of this paper are threefold: First, a new parallel algorithm for construction of the reduced visibility graph is presented. The algorithm has O(p2log(n/p)) complexity where p is the number of objects and n is the total number of vertices. Second, the mapping of the algorithm into hardware is described. Third, an efficient FPGA implementation is presented. The algorithms have been coded in VHDL and simulated using ModelSim. The designs have then been synthesized for implementation on Xilinx Virtex FPGA. Our design operates at high speed––in particular, the hardware implementation is approximately 1000 times faster than a C program implementation on a PC with Intel 1700 MHz processor and 512 MB on-board memory. Further, the implementation of a reduced visibility graph processor for 80 vertices consumes only 95% of an XCV3200E device.
The remainder of this paper is organized as follows. In the next section, we describe how shortest path computation is accomplished using the reduced visibility graph. In Section 3, we present the new parallel algorithm. Section 4 describes the architectural aspects. Implementation of the algorithm in FPGA is presented in Section 5. Conclusions are presented in Section 6.
Section snippets
Preliminaries
Some characteristics of the shortest path between a pair of points in the Euclidean plane amidst disjoint polygonal obstacles are first described. The role of visibility graphs is then presented.
Given a pair of points u and v in that are not mutually visible (the segment joining them intersects one or more objects) such that u (or v) is not on the boundary of some object, it can be shown that the shortest path between u and v goes through straight line segments between vertices that do not
Motivation
The reduced visibility graph takes less storage for a pair of polygonal objects A and B in comparison to the complete visibility graph (O(n) segments as opposed to O(n2) for the complete graph for A and B that together have a total of n vertices). However, a direct sequential algorithm for the reduced graph may have a high computational complexity (O(n2) if it is based finding a tangent to B from the vertices of A and checking if it is also a tangent to A). The proposed parallel algorithm takes
Proposed architecture
The proposed architecture is shown in Fig. 6. It consists of a memory unit, a control unit, a binary vector and obstacle check unit and a binary tree-structured comparison unit. The binary vector and obstacle check unit consists of half-plane computation units and comparators.
The details of the control unit for the overall system are shown in Fig. 7. In state S0, registers corresponding to adr and wr are initialized and the system waits for an external input rst to begin storage of data. The
FPGA implementation
The architecture presented in Section 4 has been coded in VHDL. The programs have been then simulated in ModelSim, a package for functional simulation. After the functional testing, the design has been implemented. The designs have been mapped onto a target device of Xilinx. The appropriate device has been chosen taking into consideration the number of logic blocks and pins in the device. The specifications of the target device are as follows––family: VirtexE; device: XCV3200E; speed grade: −8
Conclusions and extensions
A new algorithm and architecture for construction of the reduced visibility graph are presented in this paper. Results of implementation in Xilinx show that the hardware-based approach is approximately 1000 times faster than a C program implementation on a PC (with an Intel 1700 MHz processor and 512 MB on-board memory). Further, the design consumes only a small amount of space on the device for fairly large problem sizes.
We believe that design of algorithms with a view to map them to hardware
Dr. K. Sridharan graduated with a B.E. (Honors) from Regional Engineering College, Tiruchirapalli, India in 1987. He then received his M.S. from Indian Institute of Science, Bangalore in 1990 and his Ph.D. from Rensselaer Polytechnic Institute, Troy, New York in 1995. From March 1996 to May 2001, he was with the Department of Computer Science and Engineering, IIT Guwahati, India as an Assistant Professor. From June 2001 to December 2003, he was an Assistant Professor in the Department of
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Dr. K. Sridharan graduated with a B.E. (Honors) from Regional Engineering College, Tiruchirapalli, India in 1987. He then received his M.S. from Indian Institute of Science, Bangalore in 1990 and his Ph.D. from Rensselaer Polytechnic Institute, Troy, New York in 1995. From March 1996 to May 2001, he was with the Department of Computer Science and Engineering, IIT Guwahati, India as an Assistant Professor. From June 2001 to December 2003, he was an Assistant Professor in the Department of Electrical Engineering, IIT Madras, India. He is currently an Associate Professor in IIT Madras. He was a visiting staff member at the School of Computer Engineering, Nanyang Technological University, Singapore from May 2000 to May 2001. He has published approximately 40 papers in journals and conferences in the areas of robotics, computer vision and web-based systems. He is a Senior Member of IEEE.
T.K. Priya received the B.Tech. degree in Electrical Engineering from Calicut University, India in 1998 and the M.Tech. degree in Control Systems from Kerala University, India in 2000. She is presently working towards her Ph.D. in Electrical Engineering at Indian Institute of Technology Madras, India. Her research interests are in the areas of Algorithms and Architectures for Robotics, Computer Vision and VLSI Design.