A new Mixed Radix Conversion algorithm MRC-II

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Abstract

In this paper, we present an efficient and simplified algorithm for the Residue Number System (RNS) conversion to weighted number system which in turn will simplify the implementation of RNS sign detection, magnitude comparison, and overflow detection. The algorithm is based on the Mixed Radix Conversion (MRC). The new algorithm simplifies the hardware implementation and improves the speed of conversion by replacing a number of multiplication operations with small look-up tables. The algorithm requires less ROM size compared to those required by existing algorithms. For a moduli set consisting of eight moduli, the new algorithm requires seven tables to do the conversion with a total table size of 519 bits, while Szabo and Tanaka MRC algorithm [N.S. Szabo, R.I. Tanaka, Residue Arithmetic and its Application to Computer Technology, McGraw-Hill, New York, 1967; C.H. Huang, A fully parallel mixed-radix conversion algorithm for residue number applications, IEEE Transactions on Computers c-32 (4) (1983)] requires 28 tables with a total table size of 8960 bits; and Huang MRC algorithm (Huang, 1983) requires 36 tables with a total table size of 5760 bits.

Introduction

The Residue Number System has attracted many researchers as basis for the computational hardware in the last 60 years with an increasing interest in the last decade [1], [2], [3], [4], [5], [6], [7], [8], [9]. This system has a very big advantage in the arithmetic operations like addition, subtraction and multiplication since this system provides the ability to add, subtract or multiply without the need to wait for the carry propagation as required by the weighted number systems. A number system is weighted if there exists a set of weights wi such that for any X in the system, X can be expressed in the form ofx=i=1naiwiwhere the ai are a set of permissible digits. If the values of wi are successive powers of the same number, then the number system has a fixed base or fixed radix, e.g., base 10 or base 2. If the weights are not powers of the same radix, then the systems are called mixed-radix systems. A number is called fixed radix or fixed base system if it is a weighted number system and the values of wi are successive powers of the same number, e.g., the decimal number can be represented asX=ana1=i=1naiwiwhere0ai9andwi=10i-1In Mixed Radix, a number X may be expressed asx=i=1naiwiwhere the wi are the radices and the ai are the mixed-radix digits and 0  ai < wi. For a given set of radices, the mixed-radix representation of X is denoted by 〈an, an−1, …, a1〉, where the digits are listed in order of descending significance [1].

A residue number system is defined in terms of a set of relatively prime moduli set {m1, m2, …, mn}, that is, the GCD (mi, mj) = 1 for i  j. A decimal number X is represented by an n-tuple 〈r1, r2, …, rn〉 of its remainders with respect to each modulus in the moduli set. A remainder of a number X with respect to a modulus m is denoted by r = Xmod m or r = Xm. The Residue number system can represent any number within the range of [0, M) for unsigned numbers or -M2,M2-1 for signed numbers. Where M=i=1Nmi and is called the dynamic range [1]. Since general-purpose computers use binary number systems, therefore methods of conversion between RNS and a fixed-radix-number-system is required in order to take advantages of the RNS systems [7]. There are more than one algorithm used in the RNS-to-fixed-radix-number-system conversion process but most of them are still slow and require a large number of costly mathematical operations. Among the most used conversion methods is the Mixed Radix Conversion (MRC). MRC conversion process can perform the arithmetic using modulo mi arithmetic units. A number X is represented by mixed radices and their coefficients asX=aNi=1N-1mi++a3m1m2+a2m1+a1wherea1=|x|m1andai=xm1m2mi-1mifori>1where mi is ith mixed radix and ai is the ith coefficient. Residue Numbers can be represented in the Mixed Radix Notation by choosing the mixed radices mi to represent the moduli-set, which will cover numbers in the dynamic range M. The MRC conversion process is a lengthy one because of the high number of mathematical operations involved. A major factor in the process of simplification is the selection of the moduli set, which is an empirical procedure and an area that has not seen a lot of investigation. Another method for simplifying the conversion process depends on some conditions that can be checked while in the process of conversion, once one of the conditions satisfies, the conversion process can be terminated. These methods and others can be found in [1].

Section snippets

Understanding MRC

The new algorithm utilizes small look-up tables to eliminate some multiplication operations in the conversion process. We first consider the case where the moduli set is of size 2, and then we will explain how this algorithm can be extended easily to n-moduli set.

For a 2-moduli set (m1, m2) the number space is (m1 × m2 = M) which is called the Dynamic Range and 〈r1, r2〉 is the RNS representation of the numbers in this dynamic range where 0  r1 < m1 and 0  r2 < m2. The RNS representation of numbers between

The new MRC II

In this section, we introduce a new algorithm for RNS to decimal conversion based on the MRC conversion algorithm, denoted as MRC II.

Theorem 1

The following algorithm can be used to convert the RNS number (r1, r2, , rn) over the moduli set (m1, m2, , mn) to its decimal representationXi=aiMi-1+Xi-1for2in;n2where ai is the MRC coefficient and X1 = a1 = r1 and Mi-1=j=1i-1mj

Proof

The MRC formula for n moduli is given byX=Xn=anm1m2mn-1+an-1m1m2mn-2++a3m1m2+a2m1+a1Eq. (7) can be re-written asX=Xn=anMn-1+an-1Mn-2++a2M

MRC-II implementation

The new algorithm can be implemented with simple hardware architecture as shown in Fig. 3. Fig. 3a shows the functional diagram for calculating Xi.

For a moduli set of size 4, Fig. 3c shows the conversion process where 3 modules are needed to calculate the MRC coefficients.

The following examples illustrate the table generation and conversion process.

Example 1

For moduli set {m1, m2, m3, m4} = {8, 5, 7, 3} calculate the look-up tables needed for the conversion process:X=a4m1m2m3+a3m1m2+a2m2+a1Table (ai) can be

MRC-II hardware complexity

An iterative algorithm for computing the MRC coefficients ai and X has been described by Szabo and Tanaka [1]; its pipeline implementation is presented by Huang [9] for computing the MRC coefficients ai only. The hardware requirements and speed performance are summarized as follows:

  • (1)

    number of tables: n(n  1)/2;

  • (2)

    number of Latches: n(n + 1)/2  1;

  • (3)

    number of adders: n(n  1)/2;

  • (4)

    throughput rate: 1/(tT + tA) Hz;

  • (5)

    conversion time: (n  1)(tT + tA) or (n  1) clock cycles.

Huang [9] presented his fully parallel architecture

MRC II look-up table implementation

As we see, the look-up tables used in MRC-II are all small tables. The largest table size = MAX (mi) × log2 MAX(mi) where 1 < i  N. For modulo set used in Table 4 which has a large dynamic range of 1, 823, 277, 183, the largest modulo is only 31, i.e., the largest memory = 31 × log2 (31) = 31 × 5, which requires only 5-bit representation. These tables can be built using a combinational logic rather than using ROM. For example, Table (a2) in Example 1 can be built as follows: the table has five entries. Both the

Summary

This paper presents a new and simplified algorithm for RNS-to-decimal conversion. This algorithm is based on the MRC algorithm. It has been shown that this algorithm significantly reduces hardware complexity and makes the implementation of MRC simpler. It only requires N  1 tables with table size mi log2 mi for 1 < i  N with no assumptions on the moduli set. This novel algorithm can also be used in RNS sign detection, magnitude comparison, and overflow detection.

Mohammed Akkal received his BS degree in Computer Systems Engineering from Palestine Polytechnic University, Palestine, in 1995 and MS degree in Electrical and Computer Engineering from Wayne State University, Detroit, MI in 1996. He is currently working as a Solution Architect for Electronic Data Systems Corporation (EDS) and pursuing a Ph.D. degree in Electrical and Computer Engineering at Wayne State University, Detroit, MI. His research interests are in residue number systems and VLSI.

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Mohammed Akkal received his BS degree in Computer Systems Engineering from Palestine Polytechnic University, Palestine, in 1995 and MS degree in Electrical and Computer Engineering from Wayne State University, Detroit, MI in 1996. He is currently working as a Solution Architect for Electronic Data Systems Corporation (EDS) and pursuing a Ph.D. degree in Electrical and Computer Engineering at Wayne State University, Detroit, MI. His research interests are in residue number systems and VLSI.

Pepe Siy received his BS degree in Electrical Engineering from Mapua Institute of Technology, Philippines, in 1966 and MS degree in Electrical Engineering from University of California, Berkeley, CA in 1967, and Ph.D degree in Electrical Engineering from University of Akron, OH in 1973. He is currently a professor in the Electrical and Computer Engineering Department at Wayne State University, Detroit, MI. His current research interests are in residue number systems, sensors, high-speed hardware architectures, and VLSI.

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