A small data cache for multimedia-oriented embedded systems

Abstract

This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.

Introduction

Recently, with the dominant popularity of multimedia applications, the multimedia service delivery platforms are moving rapidly from desktop PCs to mobile platforms such as PDAs and smart-phones. As a result, multimedia devices have become one of the most growing areas in the embedded market. On the whole, multimedia applications incorporate a number of algorithms requiring the high computational complexity with heavy memory access. Therefore, the need for high performance embedded processors is increasing rapidly, simultaneously with widely spreading mobile devices. However, a unilateral approach of simply aiming at high performance could make it difficult to achieve the goal in portable multimedia devices, because they inherently have several limitations that must be considered at the design stage: low computational power, low memory area, short battery life, miniaturization requirements, real-time processing, and so on.

Multimedia embedded systems for data intensive applications require large memory bus bandwidth. However, since the memory resources and the bus bandwidth are limited, cache memories can still play an important role to bridge the performance gap between a high-speed microprocessor and low-speed main memory. Especially, considering the circumstance that datasets of multimedia applications increase in size and complexity, designing an effective and application specific memory system is becoming an important issue to efficiently move data within the memory hierarchy to reduce the overall memory access latency [1], [2]. This can be done in the optimum way by exploiting the predictable memory access patterns inherent in multimedia applications.

On conventional applications, the performance of a cache could be improved by the increase of the cache size, which can result in a high cache hit ratio. Unfortunately, in embedded systems, increasing cache capacity is not an adequate approach for high performance due to area concerns, which may increase power consumed as well as cost. The gravity of this issue can be recognized easily from the example of StrongARM 110 [3] which dissipates 42% of its total power in caches. Consequently, a small cache size is recommended for designing power efficient embedded systems. However, it may cause the issue of low cache hit rates which can decrease performance and increase power dissipation. In order to compensate the above drawback, various prefetching schemes have been proposed [4], [5], [6]. Within a limited cache space, an aggressive prefeching policy could increase cache pollution which may degrade the overall system performance. Especially in the multimedia applications, because unit-stride memory accesses may occur frequently, a policy for continual data prefetching with specialized stride intervals could be encouraged to increase overall system performance. However, it may have the possibility to introduce contiguous cache pollutions caused by data prefecthing with mismatched stride intervals.

In order to overcome these correlative memory performance issues found in data caches for multimedia embedded systems, this paper proposes a novel data cache architecture with small area combining a conventional split-cache with two hardware enhancements for prefetching and filtering. The fundamental issue is balancing all the components under a limited area to produce an energy efficient and high performance cache suitable for multimedia-oriented embedded systems. The solution is provided by exploiting the operational behaviors stemming from the algorithmic characteristics of multimedia applications. More importantly, they do not slow down the cache access, nor require excessive amount of extra hardware. The performance is evaluated with three metrics: cache size, access latencies, and energy consumption.

The remainder of this paper is organized as follows. Related work is provided in Section 2. Section 3 describes the architectural and operational characteristics of the proposed cache. Section 4 presents our simulation results on the performance and the energy consumption. Finally, conclusions are given in Section 5.