Mixed hierarchical-functional fault models for targeting sequential cores

https://doi.org/10.1016/j.sysarc.2007.07.003Get rights and content

Abstract

Current work presents a set of fault models allowing high coverage for sequential cores in systems-on-a-chip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagram based test path activation tool. According to the experiments, the proposed method significantly outperforms state-of-the-art test pattern generation tools. The main new contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to target high gate-level stuck-at fault coverage for sequential cores.

Introduction

At present, efficient methods for testing sequential cores inside the systems-on-a-chip (SoC) are missing. The hard test pattern generation task is usually replaced by theoretically much simpler approach relying on scan paths and combinational automated test pattern generation (ATPG). However, the scan-path method has its obvious shortcomings including increased area and delay, and it also causes coverage of non-functional failure modes, which results in over-testing and yield loss [1].

Several approaches to generating tests for structural faults in sequential cores have been proposed over the years. Despite of all the efforts the problem still lacks a breakthrough. At the gate-level, a number of deterministic test generation tools, both academic [2], [3] and commercial, have been implemented. None of these methods can efficiently handle sequential designs of even a couple of thousands of gates. With the further growth of the circuit size fault coverages tend to drop while run times increase rapidly.

Better performance has been obtained with simulation-based approaches. Here, genetic algorithm based methods have been widely used [4], [5], [6]. Relatively efficient results have been obtained by spectral methods [7]. However, the simulation-based methods are fast for smaller circuits only and become ineffective when the number of primary inputs and the sequential depth of the circuit increase. Moreover, these methods do not guarantee detection for hard-to-test random pattern resistant faults.

Many works on functional test generation have been published in the past [8], [9]. In this field, an efficient technique based on BDD manipulation of data domain partitions has been proposed [10]. However, the fundamental shortcoming of the approaches that rely on functional fault models only is that they do not achieve satisfactory structural level fault coverage.

Hierarchical and RTL test pattern generation has been proposed as a promising alternative to tackle complex sequential circuits. Here, top-down and bottom-up strategies are known. In the bottom-up approach [11], tests generated at the lower level will be later assembled at the higher abstraction level. Such algorithms ignore the incompleteness problem: constraints imposed by other modules and/or the network structure may prevent test vectors from being assembled. In the top-down approach [12], where constraints are extracted at the higher level with the goal to be considered when deriving tests for modules at the lower level.

Recently, a number of works have been published on implementing assignment decision diagram models [13] combined with SAT methods to address register-transfer level test pattern generation [14], [15]. The authors of this paper have been relying on a different kind of representation, called high-level decision diagrams [16], [17], where, both, control unit and datapath are handled in a uniform manner. The common shortcoming for all the former decision diagram based approaches is that they are targeting functional units in the datapath of the circuit. The main novel contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to provide for high fault coverage testing of sequential cores. Note, that although the fault models implemented in this paper are based on functional and hierarchical approaches, they are developed to target the logic-level stuck-at fault coverage of the design under test. In this work, the efficiency of test generation is measured in terms of gate-level stuck-at coverage, which is obtained by running a fault simulator tool [19].

The paper is organized as follows. In Section 2 we introduce the circuit model of high-level decision diagrams. Section 3 presents the high-level path activation process. Section 4 defines the new fault models used in current approach. Finally, experimental results and conclusions are presented.

Section snippets

Basic definitions

High-level decision diagrams (HLDD) are graph representation of discrete functions. A discrete function y = f(x), where y = (y1, …, yn) and x = (x1, …, xm) are vectors is defined on X = X1 ×  × Xm with values y  Y = Y1 ×  × Yn, and both, the domain X and the range Y are finite sets of values. The values of variables may be Boolean, Boolean vectors, integers. A high-level decision diagram Gy can be used for representing functions y = f(x).

Definition 1

A high-level decision diagram (HLDD) is a directed non-cyclic labeled graph that

High-level decision diagram based test path activation

The test generation approach proposed in current paper contains two main phases. During the first phase, called high-level test path activation, an untested module (HLDD node) is selected and for this module propagation and justification is performed. In addition, constraints for the high-level test path are extracted. The goal of the second phase is to satisfy the constraints by using a constraint solver and to compile the test patterns by assigning the values obtained by the constraint solver

Mixed functional-hierarchical fault models

In this section, we will explain the fault models implemented in current approach, where a combination of three fault models is used. These include a hierarchical fault model for functional units (FU), a functional model for multiplexers and a combined hierarchical-functional model for conditional operations. In the following we will describe each of the above models more in detail.

Experimental results

Table 1 presents the characteristics of the example circuits used in test pattern generation experiments in this paper. The following benchmarks were included to the test experiment: a Greatest Common Divisor (GCD), an 8-bit multiplier (MULT8 × 8), an Elliptic Filter (ELLIPF), an ALU based processor (RISC) and a Differential Equation (DIFFEQ). The VHDL versions of GCD and DIFFEQ were obtained from high-level synthesis benchmark suites [22], [23] and the designs of MULT8 × 8 and RISC from functional

Conclusions

In the paper we defined high-level decision diagrams (HLDD) as an efficient model for RTL test pattern generation for sequential cores. The HLDD model was compared to currently popular assignment decision diagrams. We pointed out the core benefits of the former and presented the HLDD based test path activation algorithm. The main novel contribution of this paper is the combination of the three HLDD-based fault models in order to provide for efficient and fast testing of sequential designs. We

Acknowledgements

The research has been supported partly by EC 6th framework Project STREP – IST 033709 VERTIGO, by ETF Grants G5910 and G5649 and by Enterprise Estonia funded ELIKO Technology Development Center.

Jaan Raik received his M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology in 1997 and in 2001, respectively, where he currently holds the position of a postdoc researcher. He is a member of IEEE Computer Society, a member of program committees for several top-level conferences and has co-authored more than 100 scientific publications. In 2004, he was awarded the national Young Scientist Award. His main research interests include high-level test generation and

References (24)

  • P. Maxwell, I. Hartanto, L. Bentz, Comparing functional and structural tests, in: Proceedings of the International Test...
  • H.-K.T. Ma et al.

    Test generation for sequential circuits

    IEEE Trans. CAD

    (1988)
  • T.M. Niermann, J.H. Patel, HITEC: a test generation package for sequential circuits, in: Proceedings of the European...
  • E. M. Rudnick, et al., Sequential circuit test generation in a genetic algorithm framework, in: Proceedings of the DAC,...
  • F. Corno et al.

    GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

    IEEE Trans. CAD

    (1996)
  • M.S. Hiao, E.M. Rudnick, J.H. Patel, Sequential circuit test generation using dynamic state traversal, in: Proceedings...
  • A. Giani, Efficient spectral techniques for sequential ATPG, in: Proceedings of the IEEE DATE Conference, 2001, pp....
  • D. Brahme et al.

    Functional testing of micro-processors

    IEEE Trans. Comput. C

    (1984)
  • A. Gupta, J.R. Armstrong, Functional fault modeling, in: 30th ACM/IEEE DAC, 1985, pp....
  • F. Ferrandi et al.

    Implicit test generation for behavioral VHDL models

    Int. Test Conf.

    (1998)
  • B.T. Murray, J.P. Hayes, Hierarchical test generation using precomputed tests for modules, in: Proc. ITC, 1988, pp....
  • J. Lee et al.

    Architectural level test generation for microprocessors

    IEEE Trans. CAD

    (1994)
  • Cited by (0)

    Jaan Raik received his M.Sc. and Ph.D. degrees in Computer Engineering from Tallinn University of Technology in 1997 and in 2001, respectively, where he currently holds the position of a postdoc researcher. He is a member of IEEE Computer Society, a member of program committees for several top-level conferences and has co-authored more than 100 scientific publications. In 2004, he was awarded the national Young Scientist Award. His main research interests include high-level test generation and verification.

    Raimund Ubar received his Ph.D. degree in 1971 at the Bauman Technical University in Moscow. He is a professor of Computer Engineering at Tallinn University of Technology. His research interests include computer science, electronics design, design verification, test generation, fault simulation, design-for-testability, fault-tolerance. He has published more than 200 papers and two books. R. Ubar has given seminars or lectures in 20–25 universities in more than 10 countries. In 1993–1996 he was the Chairman of the Estonian Science Foundation and a member of the Estonian Science Council. He is a Golden Core Member of the IEEE, a member of ACM, SIGDA, Gesellschaft der Informatik (Information Society, Germany), European Test Technology Technical Committee and Estonian Academy of Sciences.

    Taavi Viilukas received his Diploma and M.Sc. degrees in Computer Engineering from Tallinn University of Technology (TUT) in 2004 and in 2006, respectively. Currently he is a Ph.D. student at TUT.

    Maksim Jenihhin received his B.S. and M.Sc. degrees in Computer Engineering from Tallinn University of Technology (TUT) in 2003 and in 2004, respectively. 2004–2007 he was employed as a researcher in ELIKO Technology Development Center, Tallinn. Currently he is a Ph.D. student at TUT. He has co-authored 15 papers.

    A submission to the JSA special issue on Euromicro DSD. The authors of this paper presented a long paper and published an article in the Proceedings of the Ninth IEEE Euromicro Conference on Digital Systems Design DSD2006.

    View full text