Dual-mode floating-point adder architectures

doi:10.1016/j.sysarc.2008.05.004

Journal of Systems Architecture

Volume 54, Issue 12, December 2008, Pages 1129-1142

https://doi.org/10.1016/j.sysarc.2008.05.004 Get rights and content

Abstract

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.

Introduction

The number of transistors per chip increases rapidly due to advances in VLSI technology. Each technology generation, the feature size decreases and the die area increases. This trend makes it possible to use more sophisticated arithmetic units to increase the performance of floating-point arithmetic. As a result of this trend, many modern microprocessors provide multiple identical functional units to speed up numerical computations [37]. For example, IBM and Sun microprocessors have two identical floating-point units for addition and multiplication operations [8], [28]. Another trend is to have wide 128-bit internal datapaths [37], [41], which can support quadruple precision operands. As illustrated in [33], it is possible to have quadruple precision hardware support using a reasonable amount of hardware compared to double precision. The S/390 G5 floating point unit described in [33] implements binary and hexadecimal quadruple precision addition.

Floating-point addition/subtraction is the most frequent floating-point arithmetic operation. It requires time consuming steps such as alignment shift, addition of mantissas, leading-zero detection, normalization, and rounding. Therefore, much research has been done to develop efficient floating-point addition algorithms [7], [29], [31], [34]. In [36], an improved single-path algorithm is introduced. With this algorithm, leading-zero anticipatory logic estimates the number of leading-zeros without waiting for the sum from the mantissa adder. This approach eliminates the delay of the leading-zero detection from the critical path. Furthermore, rounding is performed in parallel with normalization to reduce the critical path delay. In [15], [30], [31], the two-path floating-point addition algorithm is introduced. With this algorithm, the datapath is divided into CLOSE and FAR paths and each path has only one massive right (alignment) or left (normalization) shifter on its critical path. Furthermore, the addition and the rounding operations are combined using a compound adder.

Even though significant research has been done to develop efficient floating-point addition algorithms, very limited research has been performed on dual-mode hardware implementations of floating-point arithmetic. Recently, dual-mode floating-point multipliers [4], [14] and a dual-mode divider [24] have been designed. A conventional floating-point addition algorithm is used to design the dual-mode quadruple precision floating-point adder presented in [3].

In this paper, dual-mode floating-point adder architectures are presented using the improved single-path and the two-path floating-point addition algorithms. First, it is shown how a double precision floating-point adder implemented with the improved single-path algorithm is modified and the datapath is divided into two parts to support both one double precision addition and two parallel single precision additions. Second, a similar technique to the one used to design the dual-mode double precision floating-point adder is used to design a dual-mode quadruple precision floating-point adder with the two-path floating-point addition algorithm. A dual-mode quadruple precision adder supports both one quadruple precision addition and two parallel double precision additions. For comparison purposes, a dual-mode quadruple precision floating-point adder with the improved single-path algorithm and a dual-mode double precision floating-point adder with the two-path algorithm are also implemented in VHDL and their synthesis results are presented in this paper. To the best of my knowledge, the dual-mode double and the dual-mode quadruple precision floating-point adders implemented with the improved single-path and two-path algorithms are the first published designs of their kind.

In designing the dual-mode adders, the overall design objective was to come up with designs that support the specified operations with a reasonable impact on area, delay, and latency. This was accomplished by taking previously published high-speed floating-point addition algorithms and hardware designs and modifying the designs to efficiently provide dual-mode functionality. In designing the dual-mode adders, special considerations were made to limit the overall increase in area by sharing hardware and limit the increase in delay by optimizing critical paths. Delay was considered to be more important than area, since the area of floating-point adders often has a small impact on the overall area of the microprocessor. In contrast if the delay of the floating-point adder is increased by too much, it may have an adverse impact on the processor cycle time, which may be unacceptable. The amount of delay increase that is acceptable will depend on the microprocessor in which the unit is being implemented.

Having dual-mode double and dual-mode quadruple precision floating-point adders is important in certain applications. For example, dual-mode double precision floating-point adders can perform two single precision floating-point additions in parallel, which is very important in multimedia applications. For example, graphics applications require intensive single precision floating-point operations [26], [42]. For extreme HD gaming, NVIDIA has developed GeForce 9800 GTX-based graphic cards that support 128 single precision floating-point operations in parallel. In addition to graphic applications, other multimedia applications such as speech recognition [11], video [21], [35], and 3D gaming [27] benefit from having parallel single precision floating-point addition. Since the dual-mode quadruple precision floating-point adder presented in this paper provides two parallel double precision floating-point additions, it speeds up applications, such as scientific computing and simulation applications, that use double precision arithmetic. Having two parallel double precision floating-point adders will also improve the performance of interval arithmetic in which each interval arithmetic addition requires two floating-point additions [5], [6]. Furthermore, having dual-mode double precision floating-point units provides support for SSE/SSE2-like instructions such as Add Packed Single-Precision Floating-Point (ADDPS) and Add Packed Double-Precision Floating-Point (ADDPD) [25], [32]. For example, two dual-mode double precision floating-point adders can perform four parallel single precision additions to support the ADDPS instruction and two parallel double precision additions to support the ADDPD instruction.

Even though double precision floating-point arithmetic is adequate for many applications, some scientific applications, such as climate modeling [17], computational physics [18], computational geometry [18], and numerical inversion of Laplace transforms using Zakian’s method [38], require more precision than double precision and double-extended precision. The necessity of high precision arithmetic is discussed in [19]. Quadruple precision arithmetic increases the accuracy and reliability of numerical computations by providing floating-point numbers that have more than twice the precision of double precision numbers. Due to the advantages of quadruple precision arithmetic in scientific computing applications, specifications for quadruple precision numbers have been added to the IEEE DRAFT Standard for Floating-Point Arithmetic [23]. To support quadruple precision arithmetic, software tools have been developed, but the main disadvantage of software tools is their speed. In [2], it is reported that software implementations of quadruple precision addition are approximately 200 times slower than quadruple precision addition implemented in hardware. Therefore, hardware support for quadruple precision floating-point arithmetic is important.

The main goals of this research are to (1) investigate how the datapath of a floating-point adder implemented with the improved single-path and two-path algorithms can efficiently be modified to provide dual-mode functionality, (2) estimate the area and the worst-case delay for each adder, and (3) present design details and critical path delays for future improvements to dual-mode adder designs.

Section snippets

Floating-point addition/subtraction algorithms

An IEEE binary floating-point number consists of three fields: a sign, S, a biased exponent, E, and a mantissa, M. The sign is 1-bit for all formats. The number of bits in the exponent is 8, 11, and 15 and the number of bits in the mantissa is 23, 52, and 112 for single, double, and quadruple precision numbers, respectively [22], [23]. The value of a normalized binary floating-point number is computed as: $V = (- 1)^{S} \times (1 . M) \times 2^{E - bias}$

Floating-point addition requires the following steps:

•
Compute the

A dual-mode double precision floating-point adder

A dual-mode double precision floating-point adder is designed with the improved single-path algorithm. The design consists of five pipeline stages. The number of pipeline stages in the dual-mode double precision floating-point adder is the same as the number of pipeline stages in the double precision floating-point adder presented in [36]. Pipeline stages 1 and 2 are shown in Fig. 1, pipeline stage 3 is shown in Fig. 8, and pipeline stages 4 and 5 are shown in Fig. 11. Since the computation of

A dual-mode quadruple precision floating-point adder

The two-path floating-point addition algorithm is used to design a dual-mode quadruple precision floating-point adder. With the two-path algorithm, the datapath is divided into CLOSE and FAR paths. The CLOSE path computes the result for effective subtraction when the exponent difference is 0 or 1. For other cases, the FAR path result is selected. Furthermore, one mantissa adder is used for each path, but they are used in different pipeline stages. Since the addition/subtraction and rounding are

Synthesis results and tests

The dual-mode double precision and the dual-mode quadruple precision floating-point adders are presented using the improved single-path and the two-path algorithms, respectively. To make a complete comparison, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using both the improved single-path and the two-path algorithms. To estimate the area and worst-case delay, all eight implementations are synthesized using LSI Logic’s

Conclusions and future work

This paper shows how a double precision floating-point adder implemented with the improved single-path algorithm and a quadruple precision floating-point adder implemented with the two-path algorithm can be modified to support both one higher precision and two parallel lower precision additions. The techniques and modifications used to implement the dual-mode double and the dual-mode quadruple precision adders are also applied to design a dual-mode quadruple precision adder with the improved

Acknowledgements

I would like to thank people at the University of Wisconsin–Madison for providing me with access to the latest software tools and resources to improve my paper. I am also grateful to the anonymous reviewers for their excellent comments on the paper.

Ahmet Akkaş received the BS degree in Electrical Engineering from Gazi University, Turkey, in 1990. From 1990 to 1993, he worked as electronics engineer at the Third Air Force Reinforcement Maintenance Base in Turkey. He received the MS and Ph.D. degrees in Computer Science from Lehigh University, USA, in 1996 and 2001, respectively. From 2001 to 2007, he worked as an assistant professor in the Computer Engineering Department at Koç University. Currently, he is a visiting faculty member in the

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^☆: This work was done when the author was with Koç University, İstanbul, Turkey and was supported by the Scientific and Technical Research Council of Turkey (TÜBİTAK) under project number 104E177.

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Dual-mode floating-point adder architectures☆