Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

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Abstract

To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.

Introduction

FPGA devices, such as Xilinx Virtex II/II Pro, Virtex 4, and Virtex 5, can be partially reconfigured at run-time, which means that one part of the device can be reconfigured while other parts remain operational without being affected by reconfiguration. Through dynamic partial reconfiguration, more and more applications can be accelerated in hardware at run-time, thus effectively reducing the overall system execution time [34]. Furthermore, much more computing intensive applications can be executed as hardware functions running on an FPGA, even though the total logic resource requirements of all hardware functions are more than those of the used FPGA devices. A hardware/software embedded system realized with such an FPGA device is called a Dynamically Partially Reconfigurable System (DPRS) that can dynamically adapt some of its hardware functions at run-time to meet different system requirements.

Through the partial reconfiguration technology, the hardware functions can be also executed as hardware tasks in an embedded operating system, similar to software tasks that can be dynamically created and removed at run-time. Such an embedded operating system that supports the DPRS architecture is called an Operating System for Reconfigurable Systems (OS4RS), using which user applications can be executed as software tasks, hardware tasks, or both according to system performance requirements. As a result, such an OS4RS design with the DPRS platform is a self-adaptable system design, in which its functionalities can dynamically change without human intervention [17].

Many existing hardware/software co-design methodologies [4], [5], [6], [12], [23], [29], [31] have proposed different effective and innovative approaches for the DPRS development; however, they only focus on parts of the DPRS development without supporting the full design and verification flow. As a result, there still exist many gaps in the DPRS development, even though they have many remarkable research results. Three main problems in most existing hardware/software co-design DPRS methodologies are described as follows:

  • 1.

    Model-platform information gap: Most UML-based design methodologies use time estimates for simulating the functional interactions between applications and a system. Furthermore, the simulation-based methods cannot guarantee that all system behaviors are tested and corrected. As a result, significantly more iterations are required for rectifying the system design, and the physical design correctness can be verified and estimated only after the UML models are synthesized into concrete system designs.

  • 2.

    Low system scalability: Reconfigurable hardware functions are usually individually implemented at design-time without supporting a unified communication interface. Therefore, to incorporate hardware functions having different data interfaces with a DPRS at run-time becomes very difficult, which does not only reduce system scalability but also increases development efforts.

  • 3.

    Limitation in infrastructure support for DPRS: Reconfigurable hardware functions are usually managed as conventional hardware devices in most DPRS design methodologies. Therefore, the enhancement of system performance using partial reconfiguration technology is still limited, and thus makes the utilization of reconfigurable hardware functions inefficient.

Besides enhancing parts of the DPRS development, if there is a more complete hardware/software co-design methodology covering effective system analysis, complete functionality verification, accurate performance estimation, and scalable system implementation, system development efforts can be further reduced. This is the motivation and also the goal of this work, in which we propose a Model-based Platform-specific Co-design (MPC) methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption. The contributions of this work are illustrated as follows:

  • The UML models proposed in MPC are designed as reusable models, using which different user applications can be effectively developed, thus significantly saving design and analysis time. The detailed DPRS behaviors specified by the UML models can be further used for model-level system verification and estimation, thus bridging the gap between high-level models and system implementation.

  • To further enhance system scalability, the concept of the layered approach is introduced in our OS4RS design. Within the hierarchical OS4RS design, we also propose a unified communication mechanism to standardize the hardware/software communication interface such that new hardware functions can be easily integrated with an OS4RS.

  • Instead of the one-to-one relation between a device node, a kernel module, and a hardware function in an embedded operating system, we propose a hardware virtualization mechanism to effectively manage the kernel resources of an operating system and the hardware logics. Thus, it is now a many-to-one or one-to-many mapping between the hardware functions configured on the FPGA and the software applications in the OS4RS user space. Using the hardware virtualization mechanism, a hardware function configured on the FPGA is virtualized such that it can be accessed by more than one application at the same time. Further, the processing results of a reconfigurable hardware function can be directly transferred to another in the kernel space, without a large time overhead in repeatedly transferring data between the user space and the kernel space.

  • We propose generic wrapper designs that can be used by hardware functions for supporting dynamic swapping. As a result, high-priority hardware tasks can interrupt low-priority hardware tasks in real-time online system environments, which can further increase the utilization of hardware logics.

The rest of the article is organized as follows. Section 2 discusses the related DPRS design methodologies. The introduction of a DPRS design is given in Section 3. Section 4 introduces the proposed MPC methodology, where Sections 4.1 Modeling and design, 4.2 Verification and estimation, 4.3 System implementation give the details of design and modeling, verification and estimation, and system implementation phases, respectively. The related experimental results and analysis are described in Section 5. Finally, conclusions are described in Section 6.

Section snippets

Related work

Similar to the development of a conventional embedded system, that of a DPRS covers three main phases, including design and modeling, verification and estimation, and system implementation phases. In the design and modeling phase, Steinbach et al. [4] proposed a complete UML-based design methodology for reconfigurable architectures to efficiently analyze the interactions between all DPRS components. Furthermore, the UML-based design methodology included a model compiler that can help designers

Dynamically partially reconfigurable system

Before introducing the proposed MPC methodology, we first introduce the design of a dynamically partially reconfigurable system (DPRS). A DPRS is a hardware/software embedded system capable of reconfiguring new hardware functions into the system at run-time, and mainly consists of a microprocessor, an FPGA, and a hardware/software communication interface. Two types of the DPRS architecture designs, namely System-on-Board (SoB)-based design and System-on-Chip (SoC)-based design as illustrated in

Model-based platform-specific co-design methodology

The target applications in this work focus on multimedia and security systems, in which computation-intensive functions are implemented as partially reconfigurable hardware tasks in an OS4RS for enhancing system performance and flexibility. As shown in Fig. 3, MPC can be separated into three phases, including modeling and design, verification and estimation, and system implementation phases. The details of the proposed MPC methodology are illustrated in the following sections.

Experiments

To illustrate how MPC can be applied to a real system, we use a Dynamically Partially Reconfigurable Network Security System (DPRNSS) as our example. DPRNSS is mainly used to support the service of Secure Socket Layer (SSL), for example, a Secure Shell (SSH) can request the DPRNSS to configure different cryptographic or hash hardware functions for data authentication and encryption/decryption, respectively. DPRNSS consists of five system devices, including a microprocessor, an FPGA, a network

Conclusions

In this work, we discovered an important characteristic of DPRS. Unlike traditional systems, the verification complexity of DPRS is limited by the amount of functionalities that can be concurrently executed in the system. This observation allowed us to successfully apply model checking to DPRS, which not only alleviates the occurrence of the state-space explosion problem to a certain degree but also increases the verification coverage at the same time. To bridge the model-platform information

Chun-Hsian Huang received his B.S. degree in Information and Computer Education from National TaiTung University, TaiTung, Taiwan, ROC, in 2004. He is currently working toward his Ph.D. in the Department of Computer Science and Information Engineering at National Chung Cheng University, Chiayi, Taiwan, ROC. He is a teaching and research assistant in the Department of Computer Science and Information Engineering at National Chung Cheng University. His research interests include dynamically

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    Chun-Hsian Huang received his B.S. degree in Information and Computer Education from National TaiTung University, TaiTung, Taiwan, ROC, in 2004. He is currently working toward his Ph.D. in the Department of Computer Science and Information Engineering at National Chung Cheng University, Chiayi, Taiwan, ROC. He is a teaching and research assistant in the Department of Computer Science and Information Engineering at National Chung Cheng University. His research interests include dynamically partially reconfigurable systems, UML-based hardware/software co-design methodology, hardware/software co-verification, and formal verification.

    Pao-Ann Hsiung received his B.S. in Mathematics and his Ph.D. in Electrical Engineering from the National Taiwan University, Taipei, Taiwan, ROC, in 1991 and 1996, respectively. From 1996 to 2000, he was a post-doctoral researcher at the Institute of Information Science, Academia Sinica, Taipei, Taiwan, ROC. From February 2001 to July 2002, he was an assistant professor and from August 2002 to July 2007 he was an associate professor in the Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi, Taiwan, ROC. Since August 2007, he has been a full professor. He was the recipient of the 2001 ACM Taipei Chapter Kuo-Ting Li Young Researcher for his significant contributions to design automation of electronic systems. He was also a recipient of the 2004 Young Scholar Research Award given by National Chung Cheng University to five young faculty members per year. He is a senior member of the IEEE, a senior member of the ACM, and a life member of the IICM. He has been included in several professional listings such as Marquis’ Who’s Who in the World, Marquis’ Who’s Who in Asia, Outstanding People of the 20th Century by International Biographical Centre, Cambridge, England, Rifacimento International’s Admirable Asian Achievers (2006), Afro/Asian Who’s Who, and Asia/Pacific Who’s Who. He is an editorial board member of the International Journal of Embedded Systems (IJES), Inderscience Publishers, USA; the International Journal of Multimedia and Ubiquitous Engineering (IJMUE), Science and Engineering Research Center (SERSC), USA; an associate editor of the Journal of Software Engineering (JSE), Academic Journals Inc., USA; an editorial board member of the Open Software Engineering Journal (OSE), Bentham Science Publishers Ltd., USA; an international editorial board member of the International Journal of Patterns (IJOP). He has been on the program committee of more than 50 international conferences. He served as session organizer and chair for PDPTA’99, and as workshop organizer and chair for RTC’99, DSVV’2000, and PDES’2005. He has published more than 150 papers in international journals and conferences. He has taken an active part in paper refereeing for international journals and conferences. His main research interests include reconfigurable computing and system design, multi-core programming, cognitive radio architecture, System-on-Chip (SoC) design and verification, embedded software synthesis and verification, real-time system design and verification, hardware–software codesign and co-verification, and component-based object-oriented application frameworks for real-time embedded systems.

    Jih-Sheng Shen received his B.S. and his M.S. in Computer Science and Information Engineering from the I-Shou University and the National Chung Cheng University, Taiwan, ROC, in 2003 and 2004, respectively. His M.S. thesis was on the design and implementation of on-chip crossroad communication architectures for low power embedded systems. He is currently pursuing his Ph.D. in the Department of Computer Science and Information Engineering at the National Chung Cheng University, Taiwan, ROC. His research interests include the theories and the architectures of reconfigurable systems, machine learning strategies, Network-on-Chip (NoC) designs, encoding methods for minimizing crosstalk interferences and dynamic power consumption.

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