A low-cost fault tolerant solution targeting commercial FPGA devices

Abstract

Technology scaling, in conjunction to the trend towards higher operation frequency, results in increased thermal stress, which in turn leads to upsets due to reliability degradation. In this paper, we introduce a software-supported framework targeting to enable sufficient fault coverage against upsets occurred due to aging phenomena. Experimental results with a number of industrial oriented DSP kernels shown the effectiveness of our framework, since we achieved average improvement in terms of maximum operation frequency and power consumption by 15% and 70%, respectively, as compared to a well-established commercial solution, for comparable fault masking.

Introduction

More than at any other time, global economics favor programmable chips over costly Application-Specific Integrated Circuits (ASICs) and Application-Specific Standard Products (ASSPs), since the costs and risks associated with application-specific devices can only be justified for a short list of ultra-high volume commodity products. Hence, programmable platforms, and more specifically Field-Programmable Gate Arrays (FPGAs), have become the only viable means for today’s companies to meet increasingly stringent product requirements – cost, power, performance, and density – in a business environment characterized by spiraling complexity, shrinking market windows, fickle market demands, capped engineering budgets, escalating ASIC and ASSP non-recurring engineering costs, and increased risk.

Recently, a number of FPGA platforms with increased performance and densities were released from reconfigurable industry (e.g. Virtex-6, Virtex-7, EasyPath series, Stratix-IV, Stratix-V, etc.) [1], [2]. Even though these devices exhibit superior system-level functionality, they still consume more power, as compared to the rest hardware implementations (e.g., ASICs, ASSPs) [3].

Meeting power, and consequently thermal budget, is an essential criterion by which customers measure the success of their FPGA-based designs. The importance of this problem becomes far more savage because power density in FPGA devices is almost doubled every three years [4], [5], [6], while this trend is expected to be increased with technology scaling according to “A-power” law [7]. Among others, higher power and thermal stress imposes that target architecture is more likely to suffer from reliability degradation, and hence to decrease the mean time between failures (MTBF) [8], [9], [10], [11]. For instance, regarding commercial grade FPGAs, the maximum die temperature without performance degradation is reported as 80 °C, whereas the absolute maximum temperature is 125 °C [3]. Furthermore, based on previously published data, an average-sized design mapped onto a Virtex-E FPGA with 90% device utilization could lead to die temperature of 50 °C above the ambient temperature value [3].

In order to highlight the importance of reliability degradation, a number of fault tolerant systems have been proposed. These solutions allow a design to continue its operation, possibly at a reduced level, rather than failing completely, when some part of the system fails.

Existing approaches in designing fault tolerant systems are applicable either in hardware, or software level. Previous analysis shown that hardware-based fault tolerance exhibits superior performance, as compared to alternative (software-based) implementations, but they impose increased fabrication cost [12], [13], [14], [15], [16], [17], [18], [19], [20]. The derived platforms exhibit static fault masking, which is defined at fabrication time. On the other hand, potentially the software-based fault tolerant solutions combine the required dependability level with the low cost of commodity devices [21], [22], [23], [24], [25].

Apart from novel methodologies, a number of CAD tools that software support these methodologies, have also to be developed [21], [22], [23], [25]. These approaches affect mainly academic solutions, while up to now the the only known commercially available framework for providing fault masking at FPGA, is the Xilinx Triple Modular Redundancy (TMR) [26]. The principle idea of TMR is the usage of hardware redundancy to mask any single failure by voting on the result of three identical copies of the circuit.

Even though available solutions, and especially Xilinx TMR, provide the maximum fault coverage both at combinational and sequential logic, the consequent mitigation cost (in terms of power consumption, delay degradation and area overhead) indicates an increased awareness that this approach is acceptable only for mission critical systems [12]. However, the technology scaling imposes that upsets due to reliability degradation are also critical for the majority of consumer products [5], [8], [9], [10]. Hence, novel techniques that could provide sufficient fault coverage with the minimum mitigation cost, are absolutely required.

As an improvement to Xilinx TMR, a number of methodologies and CAD tools have been proposed [27], [28], [29], [30], [31]. These solutions cluster hardware resources based on their sensitivity to errors, and then apply redundancy selectively only to suspicious portions of the design. Even though these approaches lead to superior performance compared to Xilinx TMR, existing solutions focus solely on masking Single Event Upsets (SEUs) [32]. On the other hand, throughout this paper, we introduce a software-supported framework, targeting both to intermediate, as well as permanent faults. The proposed solution allows selecting the maximum possible fault coverage, in respect to the application’s timing, power and area specifications.

The rest of the paper is organized as follows: Section 2 describes the motivation for this work, while Section 3 gives a number of alternative fault tolerant techniques. Section 4 introduces the proposed methodology. Experimental results that shown the efficiency of our solution are provided in Section 5. Finally, conclusions are summarized in Section 6.