Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor

Abstract

Mixed-criticality systems need to provide strict guarantees to hard real-time tasks and simultaneously, deliver high throughput for non-critical tasks. However, techniques to enhance performance more often than not affect the analyzability, e.g., caches, branch prediction, out-of-order (OoO) execution superscalar processing, and simultaneous multithreading (SMT).

In this paper, we propose the use of a polymorphic VLIW processor to increase performance for non-critical tasks while maintaining analyzability. The processor achieves these goals by dynamically distributing computing resources (in the form of datapaths) to one or multiple threads. A static schedule guarantees the minimum amount of cycles to meet the deadlines for critical tasks. Datapaths that are not used by critical tasks can be assigned to non-critical tasks in a highly flexible way, thereby increasing resource utilization resulting in higher throughput. Our experiments show that our approach can exploit its dynamic properties to improve schedulability and assign up to 50% and on average 25% more resources to lower-priority threads during the execution of a static real-time schedule.

Introduction

In modern real-time application domains, a single high-performance processor is used increasingly more often for a wide variety of tasks/workloads while having to meet restrictions regarding power, cost, size, and maintainability. The timing properties of these tasks can vary in the degree of strictness, giving rise to the field of mixed-criticality systems [1]. These systems should provide high performance but remain predictable in order to support tightly bound analyses of the worst-case execution time (WCET). Using systems with low performance (but possibly higher predictability) will limit the number of (concurrent) tasks, while systems with low predictability need to severely overestimate the WCET of its tasks to guarantee timing-safety (again limiting the number of tasks). As systems with low performance also affect the non-critical tasks, designers opt for commercial off-the-shelf (COTS) high-performance embedded platforms. These provide high performance to the lower criticality tasks during the time that the processor is not executing critical tasks. Current COTS platforms often employ heterogeneous multi-processors (HMPs), based on the ARM big.LITTLE design paradigm.

It is well-known that techniques used to improve the performance of these (superscalar) platforms, such as caches and branch prediction, have an adverse effect on the time predictability [2] causing the difference between the worst and typical execution times to increase. As the availability of these unused cycles is at the mercy of the critical tasks, they can not be trusted to be available for non-critical tasks. These non-critical tasks may not have (strict) timing requirements, but could have performance requirements, necessitating to combine them into the static real-time schedule of the critical tasks. In addition, HMPs suffer from two drawbacks. First, a tasks-cores mismatch (when N_tasks < N_cores) will result in unused cores. Second, migration of tasks from one core to another results in a penalty for saving and restoring the state (internal registers) and having to refill caches and predictors (i.e., a cold start).

In this paper, we propose to use the ρ-VEX polymorphic VLIW processor for mixed-criticality systems. It is capable of executing programs with a high level of Instruction-Level Parallelism (ILP) in a high-performance single-core 8-issue VLIW configuration, or multiple tasks or threads in a multicore configuration with smaller issue widths, allowing it to adapt to the workload. This is achieved by allowing neighboring datapaths to work independently or be combined into a single core. Independent datapaths are isolated from each other regarding performance, so they do not suffer from performance interference. The highest performing configuration provides 8 parallel datapaths, similar to the TMS320C6x family of Digital Signal Processors (DSPs) [3]. In the VLIW paradigm, all extraction of parallelism and instruction-level scheduling is pushed to the compiler. More specifically, the execution time of a ρ-VEX program is fully predictable, under the assumption that the memory subsystem that feeds the processor instructions and data is also predictable. For instance, instead of dynamic branch prediction, the compiler restructures the code after analyzing the most likely control flow. Therefore, the ρ-VEX provides a high degree of predictability without sacrificing performance for high-ILP workloads.

Moreover, in contrast to HMPs, there is no migration penalty associated with changing the power-performance trade-off point of a task in the ρ-VEX. In order to support the multicore operating modes, the ρ-VEX register file is capable of storing four separate task/thread states (virtual cores or SMT contexts) simultaneously. This also allows it to rapidly switch between programs when running in 8-way single-core mode, as long as no more than four tasks/threads are contending for processor resources. The register file design is similar to the Qualcomm Hexagon DSP processor present in current mobile chipsets [4].

In [5], the benefits of using VLIW-based polymorphism for static scheduling of real-time task graphs has been examined. This work extends upon it by providing a system architecture for mixed-criticality workloads and evaluating the advantages in terms of throughput for the non-critical tasks in the workload. In this paper, we extend our earlier work on real-time schedulability and performance on the ρ-VEX [5]. The contributions of this work are:

• We propose to use VLIW-based polymorphism as a basis to design systems for mixed-criticality workloads.

• We discuss how these systems are able to provide both temporal and spatial isolation.

• We perform an evaluation using the ρ-VEX proof-of-concept in terms of throughput using task graphs generated from the Mälardalen real-time benchmark suite.

• We show that the polymorphic VLIW is able to assign up to 50% more resources to non-critical tasks during execution of a static real-time schedule compared to heterogeneous processors with equal computational resources.

The remainder of this paper is structured as follows. Section 2 introduces the execution platform and concepts necessary to understand the work. It also discusses the scheduling methodology that provides timing isolation between critical tasks while still being able to exploit processor polymorphism to increase schedulability. Section 3 presents a system architecture providing spatial and temporal isolation, and how to exploit processor polymorphism to dynamically assign execution resources to non-critical tasks when they are not utilized by critical tasks. Section 4 discusses how we use the scheduling methodology to create valid real-time schedules for the proposed platform. Section 5 presents the evaluation setup and discusses the results, Section 6 compares this work to existing literature and Section 7 concludes the work.