Model checking of reconfigurable FPGA modules specified by Petri nets

Highlights

• Formal verification for dynamically reconfigurable logic controllers in FPGA.

• Prototyping flow supplemented by multi-stages formal verification.

• Each version of a reconfigurable module validated to avoid formal errors.

• Usage of an abstract rule-based logical model to simplify the verification process.

• Verifiable model and synthesizable VHDL code generated automatically.

Abstract

The paper proposes a novel formal verification method of reconfigurable modules implemented in FPGA devices. The modules are specified by Petri nets and can be exchanged in the already implemented and running system using dynamic partial reconfiguration. The model checking technique is used together with the abstract rule-based logical model to verify whether the new modules still satisfy the global requirements for the whole control system. The additional advantage of using the rule-based logical model is the possibility to automatically generate the VHDL code, hence the final implementation reflects the already verified specification. It allows to ensure high quality of the released product and eliminates errors related to hand-code writing. A case study is presented to illustrate the approach, as well as some experimental results.

Introduction

Control systems are undoubtedly applied not only in the industry [1], [2], [3], but recently also in everyday life, which is connected with the growing popularity of the Internet of Things systems (IoT) [4]. The usage of FPGA (Field Programmable Gate Array) devices enables the easy and efficient implementation of control processes. Additionally, the possibility of dynamic partial reconfiguration in FPGA devices [5], [6], [7], [8], [9], [10], [11] allows to exchange the modules during the runtime of the control system. So, the functionality can be changed without the necessity to stop the device. Despite the primary under-exploitation in the industrial control systems [12], the dynamic partial reconfiguration can now be found in the field of aero-space [5], [7], [13], automotive industry [8] or even medicine [9]. The reliability and high quality of the final product is here an essential aspect, as users usually fully rely on the control systems. Thus, it is important to avoid any errors and ambiguities yet at the beginning of their development, that is in the design phase [14], [15]. Model checking is an established formal verification method [16], [17] that can validate the specification against some user-defined requirements. If any of the requirements cannot be satisfied, appropriate counterexamples are generated helping to localise the possible error sources. Various specification techniques can be used to describe the designed control process [18], including Petri nets [19], [20], [21], [22] and UML (Unified Modelling Language) diagrams [23], [24], [25], [26], in particular activity diagrams and state machines diagrams.

In the paper, we propose a novel formal verification method of concurrent controllers specified by interpreted Petri nets and oriented on dynamic partial reconfiguration, based on the model checking technique. The presented idea is a significant enhancement of the previous works, especially [27] where the double model-checking method was proposed to validate the specification before and after the decomposition process, and [28] where the whole prototyping flow for logic controllers oriented on static partial reconfiguration was proposed. Here we concentrate on dynamically reconfigurable concurrent logic controllers specified by means of interpreted Petri nets, and especially on the multi-stages formal verification of specification using the abstract rule-based logical model. Not only the initial and the decomposed specification is formally verified, but also each version of a reconfigurable module is validated to avoid formal errors. Additionally, the use of the rule-based logical model simplifies the whole verification process, as both the verifiable model and synthesizable VHDL (Very High Speed Integrated Circuits Hardware Description Language) codes are generated automatically.

The rest of the paper is structured as follows. Section 2 presents shortly the state of the art. Section 3 introduces necessary definitions used in this paper. Section 4 describes the proposed multi-stages formal verification method, based on the rule-based logical model and the model checking technique. Section 5 illustrates shortly the presented approach using a simple case study. Finally, Section 6 shows some experimental results and Section 7 concludes the article.