Real-Time scheduling and analysis of parallel tasks on heterogeneous multi-cores

Abstract

Heterogeneous multi-cores and parallel architectures have recently gained much attention owing to utilizing the strength of different architectures for offering higher performance. In this paper, we study the real-time scheduling of the directed acyclic graph (DAG) tasks upon the heterogeneous multi-core platform, i.e., a task contains different types of vertices, and the workload of each vertex must execute on its particular type of cores. Traditional researches use the work-conserving scheduling strategy to schedule such a typed DAG task and lead to pessimistic schedulability tests. To this end, we propose a novel scheduling algorithm for typed DAG tasks, which assigns each vertex a varying criticality that depends on the remaining workload of the vertex, and moreover, the vertex with higher criticality is more urgent to be executed. Under this scheduling strategy, we propose a new worst-case response time (WCRT) bound to verify the schedulability of DAG task supporting heterogeneous computing. Experiments with randomly generated workload show that the accuracy of our new WCRT is about 20% higher on average than the existing bounds.

Introduction

To meet the increasing performance requirements, parallel hardware architectures have become the mainstream in the multi-cores embedded field. Parallel programming models are fundamental to exploit the performance capabilities of these architectures [1], [2], [3]. In recent years, parallel task scheduling problems with real-time constraints have made great progress [4]. Some researchers developed multiple parallel programming paradigms, such as MPI [5], OpenMP [6], [7] or parallel programming languages as CilkPlus [8] to aid developers in the creation of parallel programs. All these parallel programming paradigms currently support intra-task parallelism, where a single task consists of multiple parallel code parts that can be executed simultaneously. DAG task model is a promising model to formulate the intra-task parallelism software. The real-time scheduling and analysis of DAG parallel task model has gained a lot of attention in the real-time and High-Performance Computing communities [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18].

Moreover, heterogeneous hardware architecture that can utilize specialized processing capabilities and can offer higher performance and energy efficiency than homogeneous architecture has received more and more attention [19], [20], [21], [22], [23]. In general, heterogeneous hardware architecture consists of equipment that is asymmetric in performance and functionality [24], [25] which integrate low power general purpose multi-cores (known as the host) with specialized coprocessors (e.g., Cell/BE SPUs) or data-parallel accelerators (e.g., GPUs), such as NVIDIA Tegra X1 [26] or Xilinx UltraScale [27]. Heterogeneous multiprocessor systems on a chip (MPSoCs) as one of heterogeneous hardware architecture has been widely used in many real-time embedded systems. As introduced in [28], [29], [30] MPSoCs can be broadly classified into performance heterogeneity and functional heterogeneity. Performance heterogeneity is that cores with the same functionality (i.e., same instruction set architecture (ISA)) but different power-performance characteristics are integrated. Functional heterogeneity is that cores with very different functionality (i.e., different ISA) are interspersed on the same die. Jetson TX2 [31] belongs to performance heterogeneity since it adopts the big. LITTLE architecture [32] that integrates high-performance cores (big cores) with low-power cores (LITTLE cores). It contains two Denver cores (high-performance cores) and four ARM Cortex-A57 cores (low-power cores). Denver cores and ARM cores have different power-performance characteristics but they are coherent and share the same ISA.

Current parallel programming languages tend to support heterogeneous multi-cores. For example, in OpenMP [6], the proc_bind clause can be used to specify a mapping of threads to some processing core. In CUDA [33], the cudaSetDevice function can be used to set the following execution to the target device. In OpenCL [34], the clCreateCommandQueue function can be used to create command queues for some devices.

In this paper, we consider real-time scheduling of typed DAG tasks on heterogeneous multi-cores, where each vertex is explicitly bound to a specific type of cores for execution. Binding code snippets of a program to a specific type of cores is a common operation in heterogeneous multi-cores scheduling and can be easily implemented in mainstream parallel programming frameworks and operating systems.

The real-time scheduling of typed DAG tasks under heterogeneous platforms is studied in [35], [36], [37]. All these work schedules the DAG tasks under the work-conserving algorithm, the response time analysis methods introduced as follows. Jeffrey et al [35] proposed the first WCRT bound for the general typed DAG task model. However, Jeffrey’s response time bound is very pessimistic. Serrano et al [36] proposed the response time bound for a specific typed DAG task model with two typed cores that has certain limitations. Han et al [37] developed two response time bounds in which the first bound dominated Jeffrey’s bound [35] in analysis precision and another bound significantly improved the analysis precision by exploring more detailed task graph structure information. Even Han’s response time bounds are still very pessimistic. When analyzing the worst response time of each path, it took into account some blocked time from vertices of the same type and in different paths that have completed or not yet executed, which is unnecessary. Yang et al. [38] studied the scheduling of typed DAG tasks by decomposing each DAG task into a set of independent subtasks with artificial release time and deadlines.

This paper aims to get a more accurate WCRT upper bound for typed DAG tasks. To solve the problems in the early work, we propose a criticality allocation strategy, which assigns a criticality to each vertex. The criticality determines the urgency of vertex execution and decreases as the remaining workload of the vertex decreases. Based on the strategy, we propose a new WCRT bound to verify the schedulability of the DAG task supporting heterogeneous computing. It can reduce the number of potentially parallel vertices to a relatively small range. Experiments with randomly generated workload show that our proposed criticality allocation strategy and new bound are significantly more precise than the existing bound.

The rest of the paper is organized as follows. Section 2 discusses the related work. Section 3 introduces the system model. Section 4 enumerates the known WCRT upper bounds of the same model with us and analyzes the problems in these bounds. Section 5 presents a new scheduling strategy for typed DAG tasks based on criticality allocation. Section 6 describes the response time analysis for our new scheduling strategy. Section 7 presents the experimental results comparing our approach with existing WCRT bounds. Finally, Section 8 concludes the paper highlighting some future research directions.