Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

doi:10.1016/j.vlsi.2003.08.001

Integration

Volume 36, Issue 4, November 2003, Pages 175-189

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Abstract

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fast-settling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-μm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers.

Introduction

Power consumption is one of the most challenging issues in modern portable electronic equipment. Reduction of the power dissipation looks even more challenging in low-voltage analog integrated circuits, as there will be less room for the signal and to keep the same signal-to-noise ratio, the power is to be increased. The power consumption is also increased when the operating speed is increased. Therefore, low-power design approaches for low-voltage fast-settling operational amplifiers in switched-capacitor applications can be very attractive.

In this paper, low-power design techniques for a low-voltage fast-settling operational amplifier are discussed and a 1.5-V low-power very fast-settling operational amplifier for the first stage of a high-resolution pipelined A/D converter is presented.

First, the small-signal behavior of an Ahuja-style cascode-compensated opamp [1] is discussed. Other important parameters of the opamp including the low-frequency gain, and input-referred thermal noise are investigated as well. An optimization approach for small-signal parameters of the opamp is followed. Then, design challenges when the load capacitor is high are addressed and a fast-settling configuration proposed by the authors [2] is presented. The effect of class AB output stages on power reduction is addressed and a novel class AB output stage is presented. Then a detailed discussion on a novel approach to determine the optimum bias current of the input stage will follow. Based on the proposed approaches, a fully differential low-voltage low-power very-fast-settling opamp for use in the first stage of a 13-bit 100MS/s pipelined ADC is presented. HSPICE simulation results for this operational amplifier are presented and compared with conventional designs to illustrate the effectiveness of the proposed low-power design approaches.

Section snippets

Cascode compensation

In most high-precision applications, a relatively high gain and at the same time a large voltage swing are required for the operational amplifiers. This cannot be satisfied with only a single stage in low voltage. Therefore, two-stage or multi-stage operational amplifiers have become of more importance. In these structures, the operational amplifiers have to be compensated to be stable when a negative feedback is applied. One of the most popular compensation techniques has been the Miller

Class-AB output stage

The settling behavior of an opamp in a switched-capacitor circuit is determined by both the small-signal and large-signal settling behaviors. For the two-stage opamp of Fig. 1 it should be noted that the value of the bias current of the class-A second stage affects the value of the slew rate. It can be shown that the single-ended value of the slew rate is obtained from [7] $SR= min I_{i} C_{c}, I_{b} C_{c} +C_{load}$ where I_i and I_b are the bias current values of the input devices and the output stage. Conventionally,

Optimization of the bias current

In this section, an optimal procedure to determine the current value of the input stage and that of the output stage is presented.

The opamp architecture

Merging the approaches mentioned in the previous sections, a low-voltage low-power fast-settling operational amplifier is proposed which seems very suitable for the first residue stage of a 1.5-V 13-bit 100M-Samples/s pipelined ADC (to be seen in simulation results section). Fig. 6 shows the schematic of the proposed opamp. It uses a folded-cascode amplifier for the input stage. The proposed switched-capacitor class-AB output stage, the cascode compensation, and the presented dynamic allocation

Conclusions

In this paper, some design methodologies to reduce the current consumption of a low-voltage high-gain high-swing fast-settling operational amplifier for use in a high-resolution pipelined A/D converter were discussed. Design considerations for a cascode-compensated opamp were addressed. A novel switched-capacitor class-AB output stage was presented and an optimum dynamic allocation of settling time parameters was also presented. A 1.5-V 12-mA 80-dB gain very-fast-settling opamp driving a 10-pF

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Reza Lotfi was born in Mashhad, Iran in 1977. He received the B.Sc. degree from Ferdowsi university of Mashhad in 1997 (with honors) and the M.Sc. degree from Sharif university of Technology, Tehran, Iran, in 1999, both in Electrical Engineering. Since then, he has been a Ph.D. student in ECE department, University of Tehran. From 1998 to 2003 he was with Emad Semicon Co. Tehran, Iran, working on design of low-voltage analog and mixed-signal integrated circuits for wireless receivers. As his Ph.D. research program, he is working on design of low-voltage high-speed high-resolution pipelined analog-to-digital converters in standard digital CMOS technologies. He has been the author or co-author of several international conference papers.

Mohammad Taherzadeh-Sani was born in Mashhad, Iran in 1980. He received the B.Sc. from Ferdowsi university of Mashhad in 2001 in electronic engineering. Since then he has been a M.Sc. student in ECE department university of Tehran. As his research program, he is working on design of very high-resolution high-speed pipelined analog-to-digital converters. He has been the author or co-author of several international conference papers.

Mohammad Yaser Azizi was born in Tehran, Iran in 1977. He received the B.Sc. with the highest ranking from S. Beheshti University, Tehran, Iran in 2000. Since then he has been an M.Sc. student in ECE department university of Tehran. As his research program, he is working on design of very low-voltage high-speed pipeline analog-to-digital converters especially the non-ideal effects in the pipeline A/D converters. He has been the author or co-author of several international conference papers.

Omid Shoaei received the B.Sc. and M.A.Sc. degrees from University of Tehran, Iran, in 1986 and 1989, respectively, and the Ph.D. degree from Carleton University, Ottawa, Ont., Canada, in 1996, all in Electrical Engineering. From 1994 to 1995 he was with BNR/NORTEL, Ottawa, as a Ph.D. intern student, working on high-speed Delta-Sigma modulators. In 1995, he was with Philsar Electronics Inc., Ottawa, working on the design of a bandpass Delta-Sigma data converter. From December 1995 to February 2000, he has been a Member of Technical Staff with Bell Labs, Lucent Technologies, Allentown, PA, where he was involved in the design of mixed analog/digital integrated circuits for LAN and Fast Ethernet systems. Since 2000, he has been with Valence Semiconductor Inc., design center in Dubai, UAE, as Director of the mixed-signal group, where he has been working on pipelined and Delta-Sigma analog-to-digital converters. Dr. Shoaei has also been an assistant professor in the Department of Electrical and Computer Engineering, University of Tehran since 1999. He has received three US patents, and is the author or co-author of more than 40 international and national journal and conference publications on analog integrated circuits. His research interests include high-speed wideband as well as high-resolution analog-to-digital converters, lowpass and bandpass Delta-Sigma analog-to-digital converters, and new architectures and devices in deep sub-micron CMOS technologies for precision analog circuits.

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