Elsevier

Integration

Volume 36, Issue 4, November 2003, Pages 211-228
Integration

Capacitor matching insensitive algorithmic ADC requiring no calibrations

https://doi.org/10.1016/j.vlsi.2003.09.004Get rights and content

Abstract

A novel implementation of the algorithmic ADC is proposed in this paper. The ADC is based on an algorithmic 1.5-bit stage in which voltage multiplication is replaced by voltage addition. A floating voltage hold circuit is proposed which enables the accurate addition of signal voltages without requiring precision components. An experimental 12 bit 3.3 MS/s algorithmic ADC in 0.25 μm standard CMOS is described. It occupies 0.15 mm2 of die area and dissipates 5.5 mW. The power and area FOMs are well below those previously reported for 1.5-bit stage algorithmic ADCs.

Introduction

There is an increasing trend to embed analog-to-digital converters (ADCs) with the digital CMOS VLSI for applications requiring medium to high resolutions (10–14 bits) at sample frequencies up to a few MHz. This reduces cost, board space and board complexity, pin count and overall power consumption. For instance, such ADCs have become a ubiquitous peripheral in micro-controllers for servo applications, touch screens, measurement of supplies and die temperatures, etc.

The algorithmic or cyclic ADC [1], [2] is an excellent choice of architecture for applications where die area and power consumption are at a premium. The core of the algorithmic ADC is the 1.5-bit ADC stage which is also a common component for pipelined ADCs [3], [4] because of its high efficiency and robustness and its ability to scale easily down the pipeline [5]. The existing basic switched-capacitor (SC) charge-transfer circuit architecture for the implementation of the 1.5-bit ADC stage has not changed much in recent years [4], [6], [7]. Instead much attention is being spent on improving calibration routines for the cancellation of the effects of capacitor mismatches [8], [9], [18]. Capacitor matching is difficult to control and usually limits the resolution of the 1.5-bit stage to no more than 10 bits in standard CMOS processes.

This paper proposes a novel circuit architecture for implementing the 1.5-bit ADC stage required for algorithmic and pipelined ADCs. The voltage multiplication operations needed for such ADCs are implemented by replacing multiplication by addition. Simple techniques are presented for achieving high accuracy addition without using precision components.

Area and power figures of merit, i.e. FOMarea and FOMpower, are useful measures of the relative performance of ADCs because they compare objectively the efficiency of different design solutions. They are defined asFOMarea=A2ENOB·FSnm2/conversionandFOMpower=P2ENOB·FSpJ/conversion,where ENOB is the effective number of bits and FS is the sample frequency. There are three primary reasons for the continual improvement in efficiency of ADCs, namely shrinking technology size, improving design techniques, and novel design solutions. A comparison of recently published pipelined ADCs (year 2000 onwards) for similar technologies is shown in Fig. 1. The area and power FOMs of the current work—12-bit algorithmic ADC—are also depicted in the same diagram. FOMarea and FOMpower of the corresponding pipelined ADC, when calculated based on standard stage-to-stage scaling {1:12,14,18,18,…} [5], are each improved by a factor of 4. Indeed, the sample frequency increases by a factor of 12 while the area and power each increase by a factor of 3 (1), (2). This too is depicted in Fig. 1. It can be seen that this solution achieves the lowest area and power FOMs.

Any continuous analog voltage Va can be approximately represented in a n-bit binary form according to the following recursive algorithm [1]:Vi+1=2·Vi+Di·Vref,Di=1,Vi<0,1,otherwise,i=1,2,…,n,where V1=Va,Vref determines the input signal range Va∈(−Vref,Vref) and Di, i=1,2,…,n, is mapped onto bi, i=1,2,…,n, to give the binary representation of Va [1]: b1b2bn. Voltage Vi+1, i=1,2,…,n, in (3) is often referred to as an analog residue voltage for the ith iteration [6].

An ADC based on (3) is called an algorithmic ADC. Since (3) is recursive, the ADC is also called a cyclic ADC. A practical algorithmic ADC employing a SC circuit was first presented in [2]. In this ADC, a charge transfer technique is used to implement the arithmetic in (3) and the ADC resolution is limited by capacitor mismatch.

The charge transfer technique [2] is improved on in [6], with further circuit efficiencies presented in [10]. Digital error correction, DEC, for the removal of offsets in operational transconductance amplifiers (OTAs) and comparators, originally proposed in [11], has become an essential technique for modern algorithmic and pipelined ADCs [9], [12], including the current work. The operation of the 1.5-bit DEC is represented analytically byVi+1=2·Vi+Di·Vref,Di=1,Vi<−Vref4,0,−1,Vref4⩽Vi<Vref4,i=1,2,…,n.Vref4⩽Vi,

A block diagram of the algorithmic ADC, implemented in the course of this work, is shown in Fig. 2. The Clock Generator provides non-overlapping clocks and the Control Block allows the ADC to be configured for synchronous or asynchronous sampling. The 1.5-bit DEC block accumulates Di (4) to form a 12-bit output word. The purpose of the Algorithmic block is to perform the arithmetic of (4).

Fig. 3 is a detailed representation of the Algorithmic block. It shows a 1.5-bit (two-comparator) flash ADC, a 1-bit flash ADC for finalizing the A-to-D conversion, a 1.5-bit DAC capable of generating (−Vref,0,Vref), a S/H (sample-and-hold) and MX2 (multiply by-2) blocks. Note that Fig. 3 is an alternative representation of (4) and is common to most algorithmic ADCs. The impact of the non-ideal building blocks in Fig. 3 on the performance of the algorithmic ADC is explained in [13].

To emphasize the hardware pertaining to existing implementations, the residue transfer function is rewritten asVout=2×Vin+1×D·Vref.

The multiplier factors (1 and 2) depend on capacitor ratios in existing charge transfer hardware realizations of this equation (e.g. [14]). Charge is actively transferred from capacitor to capacitor via the virtual earth node of an OTA so that the accumulated charge on the feedback capacitor of the OTA produces Vout(5). This method is limited by the inaccuracy of capacitor matching as well as any non-linearity of capacitors. The DAC output voltages D·Vref∈(+Vref,0,−Vref) can be produced very accurately since it is sufficient to switch polarities between +Vref and −Vref or short to 0 in a differential realization. In any case, DAC errors do not affect the linearity (DNL/INL) of an algorithmic ADC.

In the method proposed here, the MX2 stage is implemented without using multiplication (i.e. charge transfer) but instead an accurate analog adder is employed. Furthermore, the DAC voltage is added without the need for charge transfer. This will be presented next.

Section snippets

Analog addition

In this section, a concept is presented for implementing the arithmetic operations (4) of the algorithmic ADC [1] in analog hardware without using multiplication. Analog multiplication, within the context of a SC circuit, is a series of voltage-to-charge and charge-to-voltage conversions—known also as the charge transfer technique (QT).

Typical concepts for creation of the MX2 function are shown in Figs. 4(a) and (c). Voltage multiplication by 2 occurs in Fig. 4(a) (C→2C) with the charge

Practical performance issues

The maximum resolution of a practical switched capacitor 1.5-bit ADC stage is limited primarily by capacitor mismatch and less so by finite amplifier gain and charge feedthrough from the switches. For the purposes of comparison of the commonly used CC and proposed C+C 1.5-bit stages, similar capacitors are assumed to be used in both cases to sample the differential input signal, Fig. 8(a).

Consider first the CC circuit in hold mode, Fig. 8(b), with all relevant parasitic capacitances included.

1.5-Bit per stage circuit implementation

The merged implementation of the 1.5-bit conversion stage of Fig. 3, comprising the S&H, Σ, MX2 and 1.5-bit DAC, is demonstrated in Fig. 9 according to the method proposed in Section 3. The ADC is fully differential, using the C+C technique developed in Section 3, with the signal range given by Vref=(RefPRefN). Assuming initially the DAC output is at RefCM, i.e. differential 0 V, then on a given cycle of the ADC, say phase 1, differential output voltage Vout=V0 is present across the series

Measurement results

The ADC was prototyped in standard 0.25 μm CMOS. A picture of the die showing the partitioning of the blocks can be seen in Fig. 13. Detailed measurements were carried out on 40 samples. The main performance parameters are presented in Table 1. The complete ADC with DEC, clocks and comparators occupies 0.15 mm2. The total power consumption including digital circuitry is 5.5 mW. Typical DNL and INL plots are presented in Fig. 14. DNL of less than 0.25 LSBs and INL of less than 0.8 LSBs at 12-bit

Conclusion

A novel implementation of the 1.5-bit ADC stage for use in both algorithmic and pipelined ADCs has been presented. Voltage multiplication has been replaced by accurate addition and a floating hold buffer has been proposed for its implementation. The accuracy of the ADC employing the new circuitry is less sensitive to the matching accuracy and linearity of the sample capacitors compared to previous circuit techniques presented in the literature.

An analytical equation has been obtained of the

Patrick Quinn received his B.E. and M.Eng.Sc degrees from the National University of Ireland, Dublin, in 1986 and 1989, respectively. From 1986 till 2000, he worked for Philips Electronics in Eindhoven, The Netherlands. There, he was initially assigned to the design of signal processing circuits for 900 MHz cellular telephones. Thereafter, he lead projects in the design of integrated CMOS and Bi-CMOS sampled-data systems for multi-standard TV and radio applications. In 2000, he joined the

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    Patrick Quinn received his B.E. and M.Eng.Sc degrees from the National University of Ireland, Dublin, in 1986 and 1989, respectively. From 1986 till 2000, he worked for Philips Electronics in Eindhoven, The Netherlands. There, he was initially assigned to the design of signal processing circuits for 900 MHz cellular telephones. Thereafter, he lead projects in the design of integrated CMOS and Bi-CMOS sampled-data systems for multi-standard TV and radio applications. In 2000, he joined the mixed-signal design team of Xilinx in Ireland, where he is lead engineer for mixed signal circuits and systems at Xilinx.

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    Maxim Pribytko received the B.S. and M.S. degrees in applied electrodynamics from the Moscow Institute of Physics and Technology (MIPT) in 1995 and 1997 respectively. He received the Ph.D. degree in electrical engineering from Trinity College, University of Dublin in 2003. At MIPT, his research was in the area of numerical electrodynamics and antenna design. At Trinity College, he was developing a novel application of capacitive sensor arrays to low power non destructive imaging. In 2000, Maxim Pribytko joined Xilinx Ireland, where he is presently a senior design engineer. His current research interests are CMOS analog and mixed signal circuits.

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