Safe integration of parameterized IP

Abstract

In order to be reused in different applications Intellectual Properties (IP) are usually parameterized. On the one hand the extensive use of parameters enables users to customize IP to their needs in different applications. On the other hand a large number of parameters imposes new problems during IP qualification, verification and integration. This article gives an overview of the present work in the IP Qualification Project (IPQ) addressing problems due to IP parameterization. We are working on solutions to handle large parameter sets, to automatically implement parameter checking, and to improve functional coverage of the parameter space. Within this scope, a novel graph-based methodology to split the parameter space into orthogonal subspaces has been devised. On the basis of a formal description of parameters and their interdependences so-called Parameter Domain Graphs (PDG) are constructed. Relying on PDG, testbench components for assertion-based parameter checking are automatically generated. Furthermore, generation constraints for verification environments are derived and collection and analysis of functional coverage data is implemented.

Introduction

The rapid development of silicon technology allows manufacturers to fabricate System-on-chip (SoC) of ever increasing complexity. Given limited human resources, time and computational power, it is unfeasible to design, verify, and test such systems from scratch. One way to deal with this problem is to include Intellectual Properties (IP) designed in-house in earlier projects or supplied by external vendors.

In order to be re-used in different applications IP are usually parameterized. On the one hand the extensive use of parameters enables users to customize IP to their needs in different applications. On the other hand a large number of parameters impose new problems during IP qualification and verification. Due to the perennial problems with the integration of IP with large parameter sets numerous concept engineers have drawn the conclusion to use such IP “as supplied” [1]. Doing so, the opportunity to re-use IP in various applications—nothing less than the basic idea behind parameterization—is given away. This article gives an overview of one part of the IP Qualification Project (IPQ) addressing problems imposed by IP parameterization. IPQ has been started in the year 2000 in order to find solutions for a wide range of IP-related problems, such as qualification, retrieval, exchange, verification, and integration [2].

Before an IP customer can select one particular parameterized IP from a large set offered by different IP vendors, he needs to determine a subset of IP suitable for his target application. Therefore, he must be enabled to select the ones that can be configured to meet the application's requirements. Providing a textual description of all parameters and their ranges—as it can usually be found included in the IP specification—does not solve the problem, since there may be illegal combinations of parameter assignments due to parameter interdependences, i.e. configurations not supported by the particular IP. In order to select valid configurations a—contingently machine-readable—representation of parameters and their interdependences is essential. For this purpose, a model to formally capture parameters including their interdependences called Parameter Domain Graph (PDG) has been devised. This model, the theory behind it, and a solution to describe parameters and their dependences are presented in 3 Theoretical framework, 4 Formal parameter definition.

During the verification process of an IP, usually a Hardware Description Language (HDL) model or netlist is simulated with different combinations of parameter assignments, i.e. simulated in different configurations. Apart from the fact that a large number of parameters make it unfeasible to verify the IP's behaviour for all configurations, it must be assured, that every configuration to be integrated into target systems is valid. Prevalent approaches, such assertions embedded into the HDL model by the IP designer or using HDL code instrumentation, e.g. offered by [3], do not represent satisfactory solutions, since they rely on RTL models and are therefore not applicable at lower abstraction levels. Furthermore, the latter approaches often create the demand for additional software tools. On the basis of the PDG model, HDL and tool independent testbench components implementing assertion-based parameter checking can automatically be generated. Thus, the necessity of additional investments is eliminated and checkers are sustained interoperable. Sections 5 through 7 depict this process in detail.

Different techniques have been introduced to achieve an acceptable coverage of the parameter space with desired distribution using randomly generated inputs in conjunction with special verification of manually defined corner cases [4]. Typically, a verification environment is used to drive stimulus data into the HDL-based IP model or netlist and to compare its response to the expected behaviour. Coverage tools are used to collect functional coverage data and help the designer to analyze that data. In order to enable random generation of IP parameters, the verification environment must be provided with generation constraints and coverage models. Section 8 shows, how generation constraints including corner emphasis and verification components for coverage collection can automatically be derived from PDG. Due to the nature of PDG in the sense of being a representation of the complete parameter space, the coverage models derived from PDG form a complete set of coverage models for the parameter space. Hence, special hole analysis techniques such as [5] become obsolete.

In order to efficiently support IP designers with the verification resp. IP users with the integration of parameterized IP, a seamless design flow integration is essential. Section 9 gives an overview and elucidates the steps to automatically create the testbench and verification components.

The complete methodology including the construction of PDG from formal descriptions, automatic generation of assertion-based parameter checking, and derivation of generation constraints and coverage collection has been implemented in the software package ParaGraph. First intended as proof-of-concept solution, later derivatives of the package have been used during the verification of a multimedia interface IP. Section 10 gives a brief description of that IP and summarizes the results.