A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Abstract

On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

Introduction

In the deep submicrometer (DSM) regime, electrical level issues that affect signalling, timing, power and noise are challenging established design procedures. Expected trends in the future evolution of VLSI systems can be codified into the following points:

• Moore's law will continue to hold for another 10 years [1].

• Single processors will not be able to utilize the transistors of an entire chip, and a single synchronous clock region will span only a small fraction of the chip area [2], [3].

• Applications will be modelled as a large number of communicating tasks, where the tasks may have very different characteristics (such as control or data flow dominated) and origins (IP re-use from earlier products or external sources) [4], [5].

An architecture that enforces modularity and is suitable for this kind of heterogeneous implementation is the Network-on-Chip (NoC) architecture [6], [7], [8]. It eases the expected bottlenecks of complexity and wire delay in nanometre technologies, and promotes extensive re-use of design cores through standardization of on-chip communication. This paper considers the physical layout of likely mesh-based NoC architectures, and carries out a feasibility study in a future 65 nm technology. Some of the issues covered are layout trade-offs and wiring schemes for the network, and area, performance and power metrics for the different architectures. The cost of the network in relation to the resources with regard to power consumption is investigated when standard rail-to-rail CMOS signalling is used.

The parameters of the 65 nm technology are obtained by following guidelines outlined in the International Technology Roadmap for Semiconductors (ITRS), and by scaling from an existing technology. Some assumptions about unknowns are made in order to facilitate analysis. This may make for a somewhat rough and ready approach on occasion, but it is adequate to provide representative figures for likely future CMOS technologies.

The rest of the paper is structured in the following manner. First the background of the NoC backbone including architecture and protocol, are reviewed in Section 2. Next the modelling details, including the physical mapping of the geometry to electrical properties and calculation of area, delay and power, are covered. Section 4 details the analysis and results for the specific architectures considered in the study. We end with a discussion.