Automatic cell placement for quantum-dot cellular automata☆
Introduction
One approach to computing at the nano-scale is the quantum-dot cellular automata (QCA) [1], [2] concept that represents information in a binary fashion, but replaces a current switch with a cell having a bi-stable charge configuration. A wealth of experiments have been conducted with metal-dot QCA, with individual devices, logic gates, wires, latches and clocked devices, all having been realized. In this article, we develop the first cell-level placement of QCA circuits. We formulate the QCA cell placement as a unidirectional geometric embedding of k-layered bipartite graphs. We then present an analytical and a stochastic solution for minimizing the wire crossings and wire length in these placement solutions. Our goal is to identify several objectives and constraints that enhance the buildability of QCA circuits and use them in our placement optimization process. The results are intended to define what is computationally interesting and could actually be built within a set of predefined placement constraints.
A QCA cell is illustrated in Fig. 1(a). Two mobile electrons are loaded into this cell and can move to different quantum dots by means of electron tunneling. Coulombic repulsion will cause the electrons to occupy only the corners of the QCA cell, resulting in two specific polarizations. The fundamental QCA logical gate is the three-input majority gate. It consists of five cells and implements the logical equation as shown in Fig. 1(b). The QCA wire is a horizontal row of QCA cells and a binary signal propagates from left-to-right because of electrostatic interactions between adjacent cells as shown in Fig. 1(c). A QCA wire can also be comprised of cells rotated . Here, as a binary signal propagates down the length of the wire, it alternates between a binary 1 and a binary 0 polarization. QCA wires are able to cross in the plane without the destruction of the value being transmitted on either wire as shown in Fig. 1(c).
Our work focus on the following undesirable design schematic characteristics associated with a near-to-midterm buildability point: large amounts of deterministic device placement, long wires, clock skew, and wire crossings. We will use CAD to: (1) identify logic gates and blocks that can be duplicated to reduce wire crossings; (2) rearrange logic gates and nodes to reduce wire crossings; (3) create shorter routing paths to logical gates (to reduce the risk of clock skew and susceptibility to defects and errors); and (4) reduce the area of a circuit (making it easier to physically build). Some of these problems have been individually considered in existing work for silicon-based VLSI design, but in combination, form a set of constraints unique to QCA requiring a unique toolset to solve them.
Section snippets
Problem formulation
QCA placement is divided into three steps: zone partitioning, zone placement, and cell placement. An illustration is shown in Fig. 2. The purpose of zone partitioning is to decompose an input circuit such that a single potential modulates the inner-dot barriers in all of the QCA cells that are grouped within a clocking zone. The zone placement step takes as input a set of zones—with each zone assigned a clocking label obtained from zone partitioning. The output of zone placement is the best
Cell placement algorithm
This section presents our cell placement algorithm, which consists of feed-through insertion, row folding, and wire crossing and wirelength optimization steps.
Experimental results
Our algorithms were implemented in C++/STL, compiled with gcc v2.96 run on Pentium III 746 MHz machine. The benchmark set consists of seven biggest circuits from ISCAS89 and five biggest circuits from ITC99 suites due to the availability of signal flow information. Table 1 shows our cell placement results where we report net wirelength and number of wire crossings for the circuits using our analytical solution and all three flavors of our Simulated Annealing algorithm. We observe in general that
Conclusions and ongoing works
In this article, we proposed a QCA cell placement problem and present an algorithm that will help automate the process of design within the constraints imposed by physical scientists. Work to address QCA routing and node duplication for wire crossing minimization are underway. The outputs from this work and the work discussed here will be used to generate computationally interesting and optimized designs for experiments by QCA physical scientists.
References (4)
- et al.
Automatic cell placement for quantum-dot cellular automata
- I. Amlani, A. Orlov, G. Toth, G. Bernstein, C. Lent, G. Snider, Digital logic gate using quantum-dot cellular automata,...
Cited by (20)
A novel configurable flip flop design using inherent capabilities of quantum-dot cellular automata
2018, Microprocessors and MicrosystemsCitation Excerpt :The QCA cell contains four quantum dots in corners of a square with two extra mobile electrons that are allowed to tunnel together between dots. The Columbic repulsion between two electrons makes the QCA cell as a bi-state device with a polarization (P) of −1 (logic value ‘0’) and +1 (logic value ‘1’) [34,35]. Two structure types of QCA cell are classified as 90° cell as shown in Fig. 2a and 45° cell as shown in Fig. 2b. QCA wires can be implemented by QCA cells that are located next to each other, the Columbic repulsion between electrons makes cells to have the same polarization as shown in Fig. 2c or to have the opposite polarization as shown in Fig. 2d [36].
Robust and efficient quantum-dot cellular automata synchronous counters
2017, Microelectronics JournalCitation Excerpt :There are two extra mobile electrons for each QCA cell which are allowed to tunnel together between dots inside the cell. The Columbic repulsion between two electrons makes the QCA cell as a bi-state device with a polarization (P) of −1 (binary logic 0) and +1 (binary logic 1) [14,15] as shown in Fig. 1. Two structure types of QCA wire are shown in Fig. 2.
Layout design of manufacturable quantum-dot cellular automata
2012, Microelectronics JournalCitation Excerpt :Initial work consisted of introducing the SQUARES formalism [4] and describing the design of a simple microprocessor [5]. Later, researchers investigated the design of general QCA circuits [6–13] as well as the design of particular QCA structures [14–18]. Certain papers focused specifically on the general design rules [19–21] which must be established as the basis of any feasible layout.
One Hybrid Strategy for Automatic Placement and Routing of QCA Circuit
2023, Tien Tzu Hsueh Pao/Acta Electronica SinicaA QCA placement and routing algorithm based on the SA algorithm
2023, International Journal of Electronics
- ☆
A short version (Ravichandran et al., 2004) is published in the Proceedings of ACM Great Lake Symposium on VLSI, 2004.