Elsevier

Integration

Volume 38, Issue 3, January 2005, Pages 541-548
Integration

Automatic cell placement for quantum-dot cellular automata

https://doi.org/10.1016/j.vlsi.2004.07.002Get rights and content

Abstract

Quantum-dot cellular automata (QCA) is a novel nano-scale computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemical molecules. In this paper we develop the first cell-level placement of QCA circuits under buildability constraints. We formulate the QCA cell placement as a unidirectional geometric embedding of k-layered bipartite graphs. We then present an analytical and a stochastic solution for minimizing the wire crossings and wire length in these placement solutions.

Introduction

One approach to computing at the nano-scale is the quantum-dot cellular automata (QCA) [1], [2] concept that represents information in a binary fashion, but replaces a current switch with a cell having a bi-stable charge configuration. A wealth of experiments have been conducted with metal-dot QCA, with individual devices, logic gates, wires, latches and clocked devices, all having been realized. In this article, we develop the first cell-level placement of QCA circuits. We formulate the QCA cell placement as a unidirectional geometric embedding of k-layered bipartite graphs. We then present an analytical and a stochastic solution for minimizing the wire crossings and wire length in these placement solutions. Our goal is to identify several objectives and constraints that enhance the buildability of QCA circuits and use them in our placement optimization process. The results are intended to define what is computationally interesting and could actually be built within a set of predefined placement constraints.

A QCA cell is illustrated in Fig. 1(a). Two mobile electrons are loaded into this cell and can move to different quantum dots by means of electron tunneling. Coulombic repulsion will cause the electrons to occupy only the corners of the QCA cell, resulting in two specific polarizations. The fundamental QCA logical gate is the three-input majority gate. It consists of five cells and implements the logical equation AB+BC+AC as shown in Fig. 1(b). The QCA wire is a horizontal row of QCA cells and a binary signal propagates from left-to-right because of electrostatic interactions between adjacent cells as shown in Fig. 1(c). A QCA wire can also be comprised of cells rotated 45. Here, as a binary signal propagates down the length of the wire, it alternates between a binary 1 and a binary 0 polarization. QCA wires are able to cross in the plane without the destruction of the value being transmitted on either wire as shown in Fig. 1(c).

Our work focus on the following undesirable design schematic characteristics associated with a near-to-midterm buildability point: large amounts of deterministic device placement, long wires, clock skew, and wire crossings. We will use CAD to: (1) identify logic gates and blocks that can be duplicated to reduce wire crossings; (2) rearrange logic gates and nodes to reduce wire crossings; (3) create shorter routing paths to logical gates (to reduce the risk of clock skew and susceptibility to defects and errors); and (4) reduce the area of a circuit (making it easier to physically build). Some of these problems have been individually considered in existing work for silicon-based VLSI design, but in combination, form a set of constraints unique to QCA requiring a unique toolset to solve them.

Section snippets

Problem formulation

QCA placement is divided into three steps: zone partitioning, zone placement, and cell placement. An illustration is shown in Fig. 2. The purpose of zone partitioning is to decompose an input circuit such that a single potential modulates the inner-dot barriers in all of the QCA cells that are grouped within a clocking zone. The zone placement step takes as input a set of zones—with each zone assigned a clocking label obtained from zone partitioning. The output of zone placement is the best

Cell placement algorithm

This section presents our cell placement algorithm, which consists of feed-through insertion, row folding, and wire crossing and wirelength optimization steps.

Experimental results

Our algorithms were implemented in C++/STL, compiled with gcc v2.96 run on Pentium III 746 MHz machine. The benchmark set consists of seven biggest circuits from ISCAS89 and five biggest circuits from ITC99 suites due to the availability of signal flow information. Table 1 shows our cell placement results where we report net wirelength and number of wire crossings for the circuits using our analytical solution and all three flavors of our Simulated Annealing algorithm. We observe in general that

Conclusions and ongoing works

In this article, we proposed a QCA cell placement problem and present an algorithm that will help automate the process of design within the constraints imposed by physical scientists. Work to address QCA routing and node duplication for wire crossing minimization are underway. The outputs from this work and the work discussed here will be used to generate computationally interesting and optimized designs for experiments by QCA physical scientists.

References (4)

  • R. Ravichandran et al.

    Automatic cell placement for quantum-dot cellular automata

  • I. Amlani, A. Orlov, G. Toth, G. Bernstein, C. Lent, G. Snider, Digital logic gate using quantum-dot cellular automata,...
There are more references available in the full text version of this article.

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A short version (Ravichandran et al., 2004) is published in the Proceedings of ACM Great Lake Symposium on VLSI, 2004.

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