Optimization of the V_T­control method for low-power ultra-thin double-gate SOI logic circuits

Abstract

Application of the V_T-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, V_CN and V_CP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V_T-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.

Introduction

Optimization of the standby power is becoming more critical as the transistor size is scaled down to nanometric dimensions. As a direct consequence of the scaling trend, the transistor off-current is being increased to accommodate for the performance scaling, as predicted by the ITRS roadmap [1]. Inherent demands of digital applications make it necessary that a digital block remains in an idle mode for a long period of time. This requirement puts forth the inquiry for more elaborate standby power optimization techniques, especially for scaled devices.

One of the well-known methods of reducing the standby power is to minimize the subthreshold leakage current when a transistor is in the idle mode [2]. This may be achieved by controlling the threshold voltage in the sense that increasing its level during the idle mode reduces the leakage current. Also, in some applications different blocks on the chip have different specifications for speed and power consumption. Dual threshold voltage scheme is usually employed to address this requirement, but it is more attractive to have a mechanism that enables the designers to optimize the threshold voltage of the transistors in different blocks.

Applying a proper voltage to the body contact has been proposed to dynamically adjust the threshold voltage of bulk MOS transistors [3]. Also, optimization of the threshold voltage adjusting technique has been studied for bulk MOSFET's [4]. However, this approach has to deal with the problem of charging and discharging the bulk capacitor, which aggravates the total delay of the circuit.

The bulk capacitor problem is eliminated in double-gate (DG) SOI structure and the back-gate may be successfully used to control the threshold voltage. Feasibility of this approach has been demonstrated by fabricating novel SOIAS structures, where the active substrate provides a potentially wide range of threshold voltage adjusting by means of proper back-gate biasing [5], [6]. The V_T-control method has been further studied by simulating various DG SOI structures for a single NMOS device and the advantage of the V_T-control method in comparison with the conventional DG operation of these devices has been addressed [7].

In this work, we are concerned with optimizing the V_T-control method for an inverter gate, which is the simplest building block of a logic circuit. Fig. 1 shows a SOI inverter in both conventional double-gate and V_T-control configurations. In the DG configuration, the front and back gates are connected to each other, whereas in V_T-control method the back gate is connected to a different voltage rather than the gate voltage, in order to control the drain–source leakage current in the idle mode. Two independent control voltages, V_CN and V_CP, are applied to the back gates of the n- and p-type transistors, respectively. When the input is low, the standby power is dominated by the n-type transistor, so a negative control voltage may be applied as V_CN to reduce the leakage current drastically. Similarly, control voltage values higher than V_DD would be needed for V_CP. This may increase the complexity of the control and pulse generation blocks. However, the n⁺–p⁺ gates presented in [7] or metal gates with different work-functions may be employed to reduce the complexity by providing further pre-adjustment capability of the threshold voltage. This optimization approach was recently introduced in [8]. In this paper, we present this method in more details. In addition, the scalability of this approach is examined and verified by extending the simulations to a group of technology generations according to the ITRS roadmap.