Low power synthesizable register files for processor and IP cores

Abstract

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks.

It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.

Introduction

In the last decade, the design methodology for complex CMOS circuits has moved from the traditional full custom design style to an automated semi-custom design flow. The main reason for these structural changes is the design productivity which must cope with the exponential increase in design complexity according to Moores Law. Even with the introduction of an automated semi-custom design flow, the ever increasing design complexity has led to the necessity of further productivity improvements, see ‘International Technology Roadmap for Semiconductors’ [1]. In order to achieve this, design reuse with synthesizable processors and IP cores has become the focus of attention in the last years [2]. These cores are implemented as soft macros applying a hardware description language (HDL) like Verilog or VHDL. The basic concept behind the reuse methodology with IP cores is a technology-independent design without any reference to the target technology. The design can be transferred easily by synthesis of the HDL model from one process technology to the next, from one ASIC vendor to another or from a semi-custom flow to a FPGA based implementation for prototyping or vice versa. This portability property is a very important aspect for this paper. In order to guarantee maximum reusability of soft macros, design rules for the HDL description are more restrictive than the rules which can be used in a semi-custom design flow in general.

As mentioned above, the design methodology changed in the last years, while at the same time the power dissipation has become a severe constraint on the physical level of a VLSI implementation due to increasing design complexity [3], [4], [5]. For mobile systems, the maximum operating time between battery recharge depends on the power dissipation of the device. For high performance systems, the costs for heat removal and packaging due to a significant power dissipation has become a major concern [6], [7]. In this paper, low power architectures of register files being part of synthesizable processors or IP cores are studied. Register files are widely used, e.g., for FIFOs, data transfer buffers, elastic buffers, memories and for the storage of state values of signal processing applications like digital filters. Another classical application of register files are processors [8]. The register files considered here, are synthesized as part of the RTL core in a semi-custom design flow. Alternatively, a RAM could be used instead. As stated in the ‘Reuse Methodology Manual’ [9] RAMs are designed on the physical level like hard macros such that they are very technology dependent. This is a contradiction to the goal of technology independence of soft macros which are the focus of this work. The portability property especially of external IP cores which an IP customer is not intended to modify is an important issue. For example, if the design including the IP cores is transferred to a FPGA prototyping environment for emulation and is finally implemented in a semi-custom product, the usage of synthesizable register files is beneficial. Therefore, synthesizable register files which are part of the design on RTL are often preferred to RAM, if the area penalty is not too high. Other reasons to prefer synthesizable register files to RAMs is the maximum achievable clock rate and further design flow issues which are discussed in detail in the Section 2.

All register file architectures discussed in this paper use clock gating for register addressing which is a standard methodology for low power register files. Clock gating is very well integrated into semi-custom design flows nowadays [10] and is often used to reduce the power dissipation of disabled modules [11], [12]. Automated clock gating inserts dedicated clock gating cells into the clock path such that edge triggered flip-flops can be disabled, if the clock input signal of the flip-flop is kept constant. The power dissipation due to changes of the data signal highly depends on the state of the clock signal of a disabled flip-flop [13]. It is shown in Section 4, that in contrast to usual sequential circuits different clock gating schemes [11] lead to significant differences in power dissipation, if they are applied to register files.

In Section 5, we propose a register file architecture using blocking logic in order to reduce power dissipation. Our method is similar to operand isolation which sets the operands or primary inputs of arithmetic units to a predefined value, if the output values are not used in the next clock cycle [11], [14]. In this work, however, we isolate the data inputs of all registers with blocking logic such that transitions of the data bus are not propagated to the data inputs of all registers such that a significant reduction of power dissipation can be obtained. This blocking logic is divided into partitions. For RAMs various concepts for partitioning are well known. For example, latest research focuses on the address logic [15], [16] but not on the data inputs as considered here.

Interleaving known from multichannel implementations of algorithms [17], [18], [19], [20] in order to reduce area and is extended to register files in Section 6. This extension is not self-evident for two reasons. Firstly, unlike an usual register file or RAM the data values cannot be accessed randomly in a register file architecture with interleaving. Secondly, the power dissipation is generally enhanced by interleaving because subsequent data samples of different channels are not correlated, see [21]. Nevertheless, it is shown here that the power dissipation of synthesizable register files with interleaving can be reduced.

This paper is organized as follows. In Section 2, the limitations on a semi-custom design flow due to IP reuse concerning low power design for register files and memory are discussed. The power dissipation of flip-flops and synthesizable register files with special emphasis on clock gating is presented in Section 3. Based on these results, three different register file architectures are proposed to reduce the power dissipation. In Section 4, we show that the application of a certain clock gating scheme is especially suited for synthesizable register files. As an alternative to this proposal, a register file architecture with partitioning is given in Section 5. Finally, for signal processing applications a register file architecture with interleaving for multichannel algorithms is examined in Section 6. It is shown that this approach can be extended to single channel applications in certain cases. The conclusions of this work are summarized in Section 7. Finally, the question is treated on whether and how the proposed register file architectures should be combined.