A parameterized graph-based framework for high-level test synthesis
Introduction
As advances are made in IC process technology, the number of transistors that can be fabricated on a single IC increases. The magnitude of the design effort also grows with circuit density. Progress in the applications of VLSI, with more than 10 millions of transistors per chip, is limited not only by circuit technology but also by the capability of the design and validation work related for such complex circuits. Therefore, we need computer-aided design tools and methods to manage this complexity.
An algorithmic synthesis tool is a computer program that transforms the high-level description of a circuit into a register transfer level (RTL) description, while at the same time, optimizing some objectives, such as area, delay, testability, reliability, and power consumption [1], [2], [3]. Traditional synthesis tools optimize area and delay only, so they produce architectures that are not necessarily optimized for testability. After that, testability strategies must be applied to RTL structure to produce a testable circuit [4], and this may produce a circuit that is not area optimized. Thus, testability should be considered as an important objective at various stages of high-level design.
The high-level synthesis (HLS) for testability aims at synthesizing an inherent testable architecture, which requires no redundancy at lower levels of abstraction. The HLS for testability is complicated due to the absence of a fault model at behavioral level that may have any obvious correlation to manufacturing defects. Therefore, several innovative methods have been presented to include sequential automatic test pattern generation (ATPG) and built-in self-test (BIST) objectives into the stages of HLS. There exist several testability parameters including sequential loop, sequential depth, controllability/observability, and self-loop that affect ATPG and BIST cost.
In this paper, a novel register allocation algorithm based on weighted graph coloring is introduced. While most high-level techniques optimize one or two high-level testability parameters including sequential depth, sequential loop, controllability/observability, and self-loop, our technique aims at optimizing these high-level testability parameters simultaneously.
The rest of the paper is organized as follows. Related works are discussed in Section 2. In Section 3, an overview of HLS and testability parameters is covered. Section 4 introduces the proposed model for register allocation, followed by Section 5 which gives some experimental results. Finally, Section 6 concludes this work.
Section snippets
Related works
A review of high-level test synthesis is presented in [5], [6], [7], [8]. The testability measures targeted by most of HLS tools for testability are mainly sequential depth, sequential loops, and controllability/observability of registers [8].
In [9], [10], [11], self-loop reduction in data path is targeted to solve problems in BIST. In [9], two allocation methods are presented to map a given scheduled data flow graph (DFG) on a self-testable data path. The first one is based on graph-heuristic
High-level synthesis
A behavioral synthesis tool usually translates the behavioral description into a suitable intermediate format, such as DFG [25]. In a DFG, each node is associated with an operation, and each edge is associated with a variable. Fig. 1 shows a partial VHDL code and its corresponding DFG, named ex1. To generate the RTL architecture, the behavioral synthesis performs two major tasks: scheduling and resource allocation.
The proposed testability model
As mentioned before, testability improvements can be performed in both register and module allocation. Although our proposed model can be used in resource allocation (both register and module allocation), we use the model only for register allocation in this paper. We construct a weighted graph whose vertices are variables and the weight of each edge shows the cost of assigning two endpoint variables of the edge to a register. We find a coloring c that minimizes function , where
Experimental results
Seven circuits were chosen to evaluate our register allocation method. We first applied our method to the DFG of each circuit for data-path synthesis, obtaining an output in Verilog format. The output is then converted to a gate-level net-list. After that the gate-level net-list is converted to ISCAS format. HITEC-PROOFS is then used to evaluate testability parameters. We assume that wco, wob, and wself are equal to 1 and all coefficients α1, …, α6 equal 10, which means all testability measures
Conclusion
Considering testability during register allocation was discussed in this paper. The controllability/observability enhancement, the ATPG time reduction, and self-loop elimination are taken into the account for register allocation and this improves fault coverage and ATPG time. We presented a register allocation method, which is based on an abstract graph model, called extended conflict graph. In our register allocation method, several testability measures including sequential depth, sequential
Saeed Safari received his B.S. degree from Sharif University of Technology, Iran in 1994, and his M.S. degree from University of Tehran in 1996. He has been a Ph.D. student in computer engineering at Sharif University of Technology since then. His research interests include SOC Synthesis, High-Level Synthesis, Test Synthesis, and CAD Tools development.
References (32)
Testing and built-in self-test—a survey
J. Syst. Archit.
(2000)- M.C. McFarland, A.C. Parker, R. Camposano, Tutorial on high-level synthesis, in: Proceedings of the 25th Design...
- et al.
The high-level synthesis of digital systems
Proc. IEEE
(1990) - S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Y. Xie, W.-L. Hung, An ILP formulation for reliability...
- et al.
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
(2000) - S. Dey, A. Raghunatan, R.K. Roy, Considering testability during high-level design, ASP DAC, 1998, pp....
- L.J. Avra, E.J. McCluskey, High-level synthesis of testable design: an overview of university systems, in: IEEE...
- et al.
High-level synthesis for testability: a survey and perspective
Proc. Des. Autom. Conf.
(1996) - et al.
High Level Test Synthesis of Digital VLSI Circuits
(1997) - S.K. Chiu, C. Papachristou, A built-in self-testing approach for minimizing hardware overhead, in: Proceedings of the...
A new approach to built-in self-testable datapath synthesis based on integer linear programming
IEEE Trans. VLSI
Cited by (0)
Saeed Safari received his B.S. degree from Sharif University of Technology, Iran in 1994, and his M.S. degree from University of Tehran in 1996. He has been a Ph.D. student in computer engineering at Sharif University of Technology since then. His research interests include SOC Synthesis, High-Level Synthesis, Test Synthesis, and CAD Tools development.
Amir Hossein Jahangir received his Ph.D. degree in Industrial Informatics from the Department of Electrical Engineering, Institut National des Sciences Appliquees, Toulouse, France in 1989. Since then, he has been with the Department of Computer Engineering, Sharif University of Technology, Tehran, Iran, where he has taught several hardware architecture courses, and supervised many M.S. and Ph.D. projects. From 1990 to 1994 he was the head of department, and has had several other academic responsibilities thereafter. His research interests include the design of high performance computer architectures, performance analysis of computer network devices, and the modeling of survivable networks.
Hadi Esmaeilzadeh received his B.S. degree from University of Tehran, Iran in 2002. He has been an M.S. student in computer engineering at University of Tehran since then. His research interests include Neural Network, Learning Theory, and SOC Testing.