Elsevier

Integration

Volume 39, Issue 4, July 2006, Pages 457-473
Integration

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design

https://doi.org/10.1016/j.vlsi.2005.08.006Get rights and content

Abstract

With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by couplings delay deterioration and crosstalk. This paper presents a timing-driven global routing algorithm along with consideration of coupling effects and crosstalk avoidance. Our work differs from the existing ones in that we design a global routing “framework” which performs well in terms of routablity, timing, and also facilitates the detailed routing in crosstalk avoidance. Experimental results on industrial circuits show that the algorithm leads to substantial delay reduction and effective crosstalk elimination.

Introduction

As the CMOS technology enters the very deep sub-micron era, the shrinking of geometries gives rise to a growing number of issues previously considered to be second-order priority for circuit designers. One of the biggest concerns is interconnect crosstalk [1], which is usually due to the capacitive coupling between the “victim” net and one or more “aggressor” nets. For 0.18 μm designs, the coupling capacitance can exceed 70 percent of the total interconnect capacitance [2] Ignoring such coupling effects may lead to significant deviations between actual and nominal timing responses, power consumptions and functional behaviors.

Previous works [3], [4], [5], [6] have made various contributions to performance-driven global routing based on conventional interconnect delay metrics [7], [8]. These algorithms are straightforward and efficient with respect to specific test cases. However, with recent advances in VDSM technology, the switching cross-coupling that by critical wires undergo becomes one of the unforeseen problems of these traditional approaches. Therefore, it is of increasing importance to consider and control coupling effects to guarantee an actual, reliable and high-performance design.

Most early works on crosstalk avoidance are focused on detailed routing [9], [10], [11], where the estimation of crosstalk is accurate but the flexibility of avoiding it is restricted. A few recent works have developed coupling-aware techniques during global routing phase. In [12], global routing with crosstalk constraints has been studied. An extended global routing problem was addressed in [13] to consider simultaneous shield insertion and net ordering with RLC crosstalk constraints. Typical methods also include post-global-route measures [14] to eliminate crosstalk. However, none of these works explicitly combine crosstalk elimination with the timing optimization problem, which remains one of the most important tasks for global routing to deal with.

A very accurate crosstalk calculation begins with detailed routing. But it is often difficult to find a crosstalk-feasible solution in detailed routing if global routing is crosstalk-blinded. The goal of this work is to develop a technique to deal with crosstalk from a global view point to decrease difficulty in obtaining crosstalk-free solution in detailed routing, while satisfying the timing constraints and routablity at the same time. Our approach works as follows: a timing-relax method is applied in the earlier phase to eliminate congestion and optimize delay simultaneously. In the later phase, a crosstalk control method is devised to find a crosstalk-feasible solution. By utilizing a conservative crosstalk model, our approach brings about crosstalk reduction by releasing the regions of high coupling “risk” with topological optimization. Our work differs from the existing ones in that we have designed a global routing “framework” which performs well in terms of routablity, and timing, and also facilitates detailed routing in crosstalk avoidance. The algorithm achieves promising results on industrial circuits.

The remainder of this paper is organized as follows: in Section 2, we formulate the global routing problem for symbolic analysis. In Section 3, the timing analysis strategy is discussed. The global routing algorithm is given in detail in Section 4. Section 5 shows the experimental results and Section 6 presents an overall conclusion.

Section snippets

Problem formulation

We first give the definition on notations. For an SC layout design, a chip is divided into a rectangular array of Mrow×Mcol cells called global routing cells (GRCs). The global routing graph (GRG) is a dual graph, which is composed of gridlines and crossings. Let G=(V,E) be the global routing graph shown by the solid line in Fig. 1. Node vi represents the center point of GRCi. The edge that links vi and vj is a GRG edge (e) with length l denoting the distance between vi and vj. A non-negative

Timing analysis

This section will give a brief introduction to the delay estimation methods.

Global routing algorithm

As mentioned earlier, our approach mainly consists of two phases. In the earlier phase, we apply a timing-relax method. A heuristic algorithm is first developed to construct the initial delay-optimal solution, followed by an optimization algorithm, which utilizes the coupling effect as a heuristic to optimize the circuit delay and congestion. Then, we devise the crosstalk control algorithm to minimize the total crosstalk.

Experimental results

We have implemented the timing-driven global routing algorithm on a Sun Enterprise 450 in C language and tested it with three industrial circuits extracted from microprocessor design. They are of 0.13 μm technology and provided with corresponding lookup tables containing the gate timing arc information. The test case data are given in Table 3. Note that the routing resource constraints had all been satisfied in the following experimental results unless specified.

Two sets of experimental data are

Conclusions and future work

Our study has shown that it is important to consider coupling effects VLSI interconnect optimization for deep sub-micron designs. We adopt advanced delay estimation models to include the lateral coupling capacitance for delay calculation. We develop a timing-driven global routing algorithm for a high-performance circuit design. By utilizing coupling as a heuristic in guiding the optimization, a substantial delay reduction has been achieved. In addition, effective crosstalk control algorithm

Jingyu Xu received her B.S. degree in Computer Science from Xi’an Jiaotong University in 1999 and her Ph.D. degree in Computer Science from Tsinghua University in 2004. She is currently a postdoctoral researcher at the EDA Lab, at the Department of Computer Science and Technology, Tsinghua University, Beijing, China. Her current research interests include algorithms for VLSI automation design, especially performance-driven routing.

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Cited by (4)

Jingyu Xu received her B.S. degree in Computer Science from Xi’an Jiaotong University in 1999 and her Ph.D. degree in Computer Science from Tsinghua University in 2004. She is currently a postdoctoral researcher at the EDA Lab, at the Department of Computer Science and Technology, Tsinghua University, Beijing, China. Her current research interests include algorithms for VLSI automation design, especially performance-driven routing.

Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. He was a Visiting Scholar at the University of California, Berkeley, and worked in the research group of Prof. E. S. Kuh from April 1991 to October 1992 and from June to September 1993. Since 1988, he has been a professor at the Department of Computer Science and Technology, Tsinghua University. His research interests include layout algorithms and systems. He was the Chief Designer of national projects for the second-generation and third-generation VLSI CAD system (PANDA) in China. He is also an IEEE fellow.

Tong Jing received the B.S. degree in EE and the M.S. and Ph.D. degrees in CS from Northwestern Polytechnical University, Xi’an, China, in 1989, 1992, and 1999, respectively. From September 1999 to April 2001, he was a Postdoctoral Researcher of the EDA Laboratory in the CST Department, Tsinghua University, Beijing, China. Since 2001, he has been a Faculty Member in the CST Department at Tsinghua University, where he is currently an Associate Professor. He was a Visiting Scholar in University of California, San Diego and Chinese University of Hong Kong. He has authored or coauthored more than 90 papers published in technical journals and conference proceedings. His research interests include routing, Steiner problem, interconnect optimization, and combinatorial problem. Dr. Jing is a recipient of the IEEE/ACM ASP-DAC Best Paper Award in 2005, ACM/IEEE ISQED Best Paper Candidate in 2005, and IEEE ASICON Outstanding Student Paper Award in 2003. He is a recipient of the First Class Award for Excellence in Teaching from Beijing in 2004 and the First Class Award for Excellence in Teaching from Tsinghua University in 2002 and 2004. He has served as a TPC member of the 2006 IEEE/ACM ASP-DAC; the Secretary General and Chair of Physical Design and Interconnect Optimization TPC Subcommittee of the 2005 ASP-DAC; the Session Chair of the 2005 IEEE ASAP; a TPC member of the 2005 IEEE ASICON; a TPC member, a Panel Speaker, and Session Co-Chair of the IEEE ICCCAS 2004; a Session Chair of the ISCI 2004; the Secretary General and TPC member of the 2003 IEEE ASICON; and the Session Co-Chair of the 2003 IEEE/ACM ASP-DAC.

Ling Zhang received her B.S. degree in Electronic Engineering, and her M.S. degree in Computer Science from Tsinghua University in 2002 and 2004, respectively. Her research interests include VLSI layout, especially performance optimization routing.

Jun Gu received his B.S. degree in Electrical Engineering from the University of Science and Technology of China in 1982 and his Ph.D. degree in Computer Science from the University of Utah in 1989. He was a professor at Calgary University in Canada and he is currently a professor of the Department of Computer Science at the Hong Kong University of Science and Technology. His research interests include optimization algorithms, local search and global optimization, and their application in VLSI CAD, system engineering, communication and multi-media fields.

This work was partially supported by National Natural Science Foundation of China (NSFC) under Grant No. 60373012, Specialized Research Fund for the Doctoral Program of Higher Education (SRFDP) of China under Grant No. 20050003099, and the Hi-Tech Research and Development (863) Program of China under Grant No. 2004AA1Z1050.

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