LFSR multipliers over GF(2^m) defined by all-one polynomial

Abstract

This paper presents two bit-serial modular multipliers based on the linear feedback shift register using an irreducible all one polynomial (AOP) over GF(2^m). First, a new multiplication algorithm and its architecture are proposed for the modular AB multiplication. Then a new algorithm and architecture for the modular AB² multiplication are derived based on the first multiplier. They have significantly smaller hardware complexity than the previous multipliers because of using the property of AOP. It simplifies the modular reduction compared with the case of using the generalized irreducible polynomial. Since the proposed multipliers have low hardware requirements and regular structures, they are suitable for VLSI implementation. The proposed multipliers can be used as the kernel architecture for the operations of exponentiation, inversion, and division.

Introduction

Finite field arithmetic is a fundamental to the implementation of a number of modern cryptographic systems and schemes [1], [2]. The performance of the cryptosystems is primarily determined by an efficient implementation of the arithmetic operations (addition, multiplication and inversion) in the underlying finite field [3]. Inversion can be carried out using just two modular AB multipliers or a power-sum (AB² multiplication) architecture. Therefore, to reduce the complexity of elliptic curve cryptosystems, efficient architectures for both AB and AB² multiplications over GF(2^m) are necessary.

Several architectures have already been developed to construct the low complexity bit-serial and bit-parallel multiplications using the irreducible AOP [4], [5], [6], [7], [8]. In 1989, Itoh and Tsujii designed two low complexity multipliers based on AOP and the irreducible equally spaced polynomial [4]. Since the multipliers have been proposed, many bit-serial and bit-parallel low complexity multipliers have been proposed for cryptographic applications. To decrease the computation complexity, Koc and Sunar designed multipliers with a low complexity, which requires m² AND gates and m²−1 XOR gates [6]. In 1997, Fenn et al. presented two bit-serial multipliers using linear feedback shift register (LFSR) architecture with a low area complexity [5]. Liu et al. in [7] and Lee et al. in [8] proposed bit-parallel AB² multipliers with systolic architecture, respectively. Kim et al. presented two bit-serial multipliers, a modular AB multiplier and a modular AB² multiplier, using LFSR architecture based on the inner-product with a very simple hardware complexity [9]. Jeon et al. also proposed LFSR AB² multipliers using the property of the inner-product [10]. Although Kim et al.'s in [9] and Jeon et al.'s in [10] simplified their hardware complexity, they still require one additional modular reduction after their operation due to that they gave results over the extended polynomial basis not over the polynomial basis.

The purpose of this paper is to propose two bit-serial multipliers with an irreducible AOP over GF(2^m) using LFSR architecture. First, a new architecture for AB modular multiplication is designed with a new multiplication algorithm. Then a new algorithm and architecture are implemented for AB² modular multiplication. They require 2m+1 clock cycles and have smaller hardware complexity than the previous LFSR architectures. The proposed multipliers can be used as a kernel circuit for exponentiation, inversion, and division architectures. They are easy to implement VLSI hardware and could be used in IC cards as they have a particularly simple structure.