Elsevier

Integration

Volume 40, Issue 4, July 2007, Pages 536-548
Integration

Integrating firewire peripheral interface with an ethernet custom network processor

https://doi.org/10.1016/j.vlsi.2006.09.003Get rights and content

Abstract

Bandwidth demands on ubiquitous Ethernet have grown immensely, driven by the rapid expansion of real-time applications like audio/video streaming. In a related research, the authors designed a novel high-performance custom network processor chip using field programmable gate arrays (FPGAs). The main function of this chip (named SPEED) is to bypass the operating system processing of network protocol stack at the host computer by off-loading its networking functions to hardware. This simplification is not only required to fit in a hardware solution, but also it improves network performance. The novel chip utilizes the concept of Ethernet channels, where Ethernet frames are addressed in a multicast addressing scheme.

In this article, we integrate the chip with a Firewire peripheral interface (FPI). A crucial function of the FPI design is to convert the IEEE 1394 isochronous traffic to the Ethernet frame format via two independent asynchronous write and read buffers. The FPI also manages the SPEED hardware interrupt signals in a bi-directional communication scheme. The goal of this research is to map isochronous Firewire packets into Ethernet frames by utilizing the SPEED Ethernet channel assignment capability. We used Verilog Hardware Description Language (HDL) to synthesize the FPI design. Since the FPI needs to support bi-directional communication, we also present a generic HDL model for bi-directional data sharing, which can be used in similar bi-directional applications.

Initial performance measures show that the FPI consumes less that 0.15 W of power. Also we found that the synthesized design utilizes only 28% of the target chip resources. Hence it was possible to incorporate it with the SPEED design in the same FPGA chip. This low power consumption will lead to powering SPEED-FPI based network devices through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. Thus, the SPEED-FPI system reduces the installation complexity, especially for large number of devices (e.g., surveillance cameras).

Introduction

The IEEE 1394 (Firewire) high-speed interface enables simple, low-cost, high-bandwidth real-time data connectivity between computers, and digital devices [1]. Today, all major PC makers provide customers with the option of adding IEEE 1394 to both desktop and notebook PCs. The 1394–1995 is an IEEE designation for a high-performance serial bus [2]. A first revision to this standard was published as IEEE 1394a–2000 [3]. The 1394b standard increased the speed of 1394a to 800, 1600, and 3200 Mbps, as well as provided new connection options such as plastic and glass optical fibers [4].

The bandwidth capacity of the IEEE 1394 displace most other peripheral connection communication methods in use today, including parallel port, RS232, SCSI, USB, and consolidate them into a unified high-performance serial bus [5], [6], [7].

The IEEE 1394 architecture involves three layers; physical, link, and transaction layers. The physical layer (PHY) connects to the cable, transfers electrical signals to serial logical symbols, and delivers to the link layer controller (LLC) parallel transmit/receive data. The LLC in turn provides data checking, and framing. Asynchronous data are delivered by the transaction layer to the application. However, isochronous, real-time, data are delivered directly by the LLC to the application.

Fig. 1 shows the topological relationship between the three layers of IEEE 1394, where the transaction layer is implemented in the host operating system. The IEEE 1394 PHY has from one side the 3 twisted pair of the IEEE 1394 cable. On the other side of the PHY is 8-bit bi-directional data bus (D0–D7) and two-bit control bus (CTL) for link layer interface. The SYSCLK frequency of 49.152 MHz is provided by PHY to synchronize with the LLC internal circuit. The two bi-directional CTL signals control communication between the PHY and the LLC. The LLC uses LREQ input to initiate a service request to the PHY.

In recent research studies testing the Ethernet and Firewire network behaviors, it was found that IEEE 1394 delivered data rate is limited by the computer PCI bus handling through operating systems. This limitation is reported to a best case of 25% of the maximum bandwidth. Worse results were reported for the Ethernet were the ratio drops to 10% [8], [9]. Hence, network traffic passing through computer I/O ports is available only at a minor portion of the computer's time, which is by far unacceptable, especially for real-time applications. One essential solution was to improve the computer's way it handles its local bus, and I/O ports. Another device-oriented solution is to embed sophisticated processors, along with their memory system in the device. The later solution is device dependent and should be amortized by the volume of the device production and the high data-rates it requires. Although it uses less power than a computer but it still consumes high power. For example, in peer-to-peer industrial data communications [10], a system design for factory automation equipment is designed, where a FPGA chip is used to interface IEEE 1394 isochronous data between embedded LLC and PHY and the application through DRAM or FIFO. There are several FPGA solutions for IEEE 1394 using reusable synthesizable PHY cores targeted to FPGA like for example in [11], [12], [13].

Other research studies have focused on comparing Firewire with the Ethernet [14], [15], where it was found that the Ethernet is suitable for best-effort asynchronous packet switching, whereas Firewire is more suitable for audio/video streaming with a guaranteed minimum bandwidth and a maximum latency. Both protocols can be used in backbone network application [16], [17], although their topologies will be different. Namely, most Ethernet topologies are based upon a star configuration, where the center node is the Ethernet switch. Meanwhile, in the Firewire technology, there is no center node, and the typical topology is tree shaped. Also, the node identification is done in Ethernet via a unique MAC address, while in Firewire node identification is determined dynamically by an arbitrary bus reset signal. Both enhanced Ethernet and Firewire technologies now provide power through data cables. Both interfaces are made available by either an expansion card (in desktops PCs) or an integrated component (in laptop computers).

Clearly, there is a pressing need for an efficient embedded system, which consumes less power, and has flexible features (i.e., easily programmable). Hence the authors designed a hardware core, called SPEED, which implements Ethernet channeling at the link layer [18], [19]. Since the problem in the IEEE 1394 is very similar to Ethernet bandwidth bottlenecks, we present in this paper how we expand the idea of directly transferring the network traffic at the link layer to the IEEE 1394 Firewire network, i.e., without needing to connect to a host computer system. An important design decision made here is to eliminate the use of a general-purpose microprocessor or network processor because current network processors can consume as much as 16 W of power [20], [21].

The rest of the paper is organized as follows. Section 2 gives a general overview of the SPEED system architecture, including the illustration of the link layer Ethernet channeling. Section 3 presents the system architecture and shows how the proposed Firewire peripheral interface (FPI) interfaces with SPEED system. Section 4 gives the design and specifications of the proposed FPI, such that it meets the requirements of the SPEED interrupt signals. Section 5 presents simulation results and output waveforms of the designed FPI, followed by synthesis results in Section 6. Timing analysis, power analysis, and further discussions are done in Section 7. The paper concludes in Section 8 with summary and suggests potential areas of future work.

Section snippets

Overview of SPEED architecture

Since the standard design of IEEE 1394 LLC, shown in Fig. 1, does not support direct hardware interfaces other than to the IEEE 1394 PHY or to the host PC, we could not use the synthesizable cores ready made for IEEE 1394 LLC, and we needed to design a custom FPI to interface with the SPEED chip. In this section we will have a general overview of the SPEED chip.

One of the SPEED-Core main functions is to do a customized link layer realization of the Ethernet media access layer (CMAC), which

Proposed SPEED-FPI architecture

The main function of the FPI module is to initiate packet transmit and receive operations according to two hardware interrupt signals; the PKdone and the TXEN signals. The management of these interrupts is shared between the FPI and SPEED cores. In particular, the main functions of FPI are:

  • to support SPEED Core with transmit/receive data through the two-shared FIFO buffers,

  • to respond to the SPEED Core input PKDone interrupt signal,

  • and to initiate a TXEN interrupt signal to the SPEED Core upon

FPI design specification

The FPI design is divided into two modules; receive and transmit modules. The SYSCLK signal of 49.152 MHz is the timing signal for both modules, which is having a clock cycle of approximately 20.345 ns. The minimum time delay required by the PHY between the edge of SYSCLK and a change in CTL or data lines is 2 nano seconds (ns) to avoid unstable race conditions in asynchronous circuit inputs.

To avoid such instability, both the FPI receive and transmit modules are timed with the negative edge of

FPI simulation and output waveforms

Fig. 11 shows Verilog simulation waveforms of the FPI. The first signal shown is the SYSCLK periodic signal of cycle time about 20 ns. The CTL and D signal values are represented as hexadecimal numbers. After about 95 ns from simulation start the CTL lines are set by the PHY to receive status, (CTL=2 or 10 in binary), and the data on condition (D=ff) is set. Therefore, the FPI receive module is asserts the TXEN interrupt and enters the data on state and proceeds to the link speed state. According

FPI synthesis results

We used Verilog HDL tools to synthesis our FPI design into a Ql4036 FPGA chip of 208 pins. Fig. 12 shows a synthesized FPI with all connection paths drawn as connection lines between the cells. Out of 672 available unbuffered/buffered cells, the design used 49 unbuffered, 76 buffered cells, and 25 Flip-Flops. The computed cell utilization is 7.3% and 11.3% of un-buffered and buffered cells respectively. Utilized routing resources were 28%. Chip total power consumption was computed by the

Timing analysis

The minimum time delay required by the PHY between the edge of SYSCLK and a change in CTL or data lines is 2 ns to avoid unstable race conditions in asynchronous circuit inputs. To achieve this, we used a half cycle delay to allow the CTL and data lines transition delay of about 10 ns, which is half of the 20 ns SYSCLK cycle time. We eliminated the need of a special delay circuit in the FPI, but added a small cost of extra 8 ns delay. This 8 ns delay is applied once for a full packet transmission

Experimental setup

Shown in Fig. 14, the developed prototype used to test the concepts of this research. Two copies of the prototype were used to connect two remote Firewire buses using an interconnecting 100 Mbps, non-dedicated Ethernet VLAN. A priority based VLAN is assigned a high priority for all packets encapsulating Firewire isochronous streams. Firewire isochronous manager is set at one side of the VLAN, which is responsible to maintain timing of the CycleStart frame, every 125 μs. At the other end of the

Conclusion and future work

We presented the design, synthesis, and analysis of a cost effective Firewire peripheral interface (FPI) to the SPEED system using FPGA chip and presented simple Verilog modeling of bi-directional signals.

The main functions of FPI are to communicate with a IEEE 1394 Physical layer chip, and a SPEED Core, or a SPEED core to deliver data packets to both ends. Two buffers are used for the input and output paths. The conversion of raw data into packets in the buffer and vise versa is done by the

Dr. Elkeelany received the B.S. and M.S. degrees in Computer Science and Automatic Control from the University of Alexandria, Egypt, 1992 and 1998, respectively. In 1999, he joined the University of Missouri-Kansas City (UMKC) to pursue his Ph.D. degree in Engineering and Networking disciplines. He focused on embedded systems design for computer networks. He also served as an adjunct faculty of electrical engineering for the UMKC. While being a Ph.D. student at UMKC, he joined Broadband

References (21)

  • O. Elkeelany et al.

    SPEED: stand-alone programmable Ethernet enabled devices

    J. Microprocess. Microsyst. JM&M

    (2004)
  • O. Elkeelany et al.

    Direct connect device core: design and applications

    Integrat. VLSI J.

    (2004)
  • Texas Instruments, IEEE 1394 Technical Overview,...
  • IEEE Standard for a High Performance Serial Bus 1394–1995, IEEE Press,...
  • IEEE Standard for a High Performance Serial Bus—Amendment 1 1394a–2000, IEEE Press,...
  • 1394 Trade Association, Grapevine, TX, USA...
  • M.A. Mazidi et al.

    The 80×86 IBM PC and Compatible Computers

    (2000)
  • W.L. Rosch

    The Winn L. Rosch Hardware Bible

    (1999)
  • A. Franaszek, X.W. Peter, Albert, Byte oriented DC-balanced (0,4) 8B/10B partitioned Block transmission code, US patent...
  • R.C. Norris et al.

    Comparing the performance of IP over Ethernet and IEEE 1394 on a Java platform

    Proc. IEEE Pacific Conf. Commun. Comput. Signal Process.

    (2001)
There are more references available in the full text version of this article.

Cited by (0)

Dr. Elkeelany received the B.S. and M.S. degrees in Computer Science and Automatic Control from the University of Alexandria, Egypt, 1992 and 1998, respectively. In 1999, he joined the University of Missouri-Kansas City (UMKC) to pursue his Ph.D. degree in Engineering and Networking disciplines. He focused on embedded systems design for computer networks. He also served as an adjunct faculty of electrical engineering for the UMKC. While being a Ph.D. student at UMKC, he joined Broadband Wireless Group of Sprint Incorporation for a six-month research project on portability and mobile nodes.

Dr. Elkeelany has a distinguished educational record, being the recipient of the UMKC Outstanding Doctoral Interdisciplinary Ph.D. Student Award in 2004, the UMKC Chancellor's Interdisciplinary Ph.D. Merit Award in 2001–2002 and the UMKC Outstanding Graduate Student Award from the School of Engineering, during 1999, 2000 and 2002. He received his B.S. degree with distinction and degree of honor. In May 2004, he received the Ph.D. degree and joined the research team of Wideband Corporation in Independence, MO, where he worked in the design and development of layer 3 network routers. In May 2005, Dr. Elkeelany received the Doctor of Research degree from the International Institute of Science and Technology.

Dr. Elkeelany has expertise in the fields of embedded system design and computer networks. His Ph.D. research contribution has been on the design of low-power remotely programmable Field Programmable Gate Array (FPGA) chips for Direct Connect Devices. In Sprint, Inc. during a six-month research project, his research contribution has been in a design of a novel architecture for remote-access wireless Virtual Private Network (VPN), which adopts authentication and registration protocols to support remote-access VPN services over high-speed wireless networks. In Wideband Corporation, his contributions have been on the design of a Secured Gold USB key for privacy protection, and on layer 3 secured Gigabit intelligent switches. Dr. Elkeelany played a pioneering role to design routing features of these layer 3 intelligent switches in conjunction with the Network Management Unit, which exploits embedded processors to manage network functions completely and efficiently in hardware. The Network Management Unit, of Wideband Corporation, was successfully launched as a commercial product in 2006.

In August 2005, Dr. Elkeelany joined Tennessee Tech University as an Assistant Professor. Dr. Elkeelany's research is in the areas of Embedded Systems for Computer Networks, Network Security, Data Streaming, Performance Analysis of Computer Networks using Simulation Models, Design of High-speed Network Devices and the use of Hardware Description Language in building new efficient designs. Since he joined Tennessee Tech University, Dr. Elkeelany worked hard to establish the Embedded Systems Design Laboratory, in Brown Hall 411. This lab enables multiple embedded systems research and adds to the education program for both undergraduate and graduate students. Dr. Elkeelany is a member of the Institute of Electronic and Electrical Engineers (IEEE), the IEEE Computer Society, and the Eta Kappa Nu Honorary Society. He is the faculty advisor for the Tennessee Tech University—IEEE student chapter.

Prof. Ghulam M. Chaudhry, B.S., University of Punjab, Pakistan; M.S., Wayne State University, University of Multan, Pakistan. He holds the Ph.D. Wayne State University-Detroit, 1989. Currently, he is a professor of Division of Computer Science and Electrical Engineering in the School of Computing and Engineering, University of Missouri-Kansa City. Areas of research interest are Computer Architecture and Parallel Processing, Performance of Multiprocessor Systems, Digital System Design, Neural Network Applications, Computer Network Management, ATM Architecture and Performance, and Verilog HDL. Among different other awards, he is the recipient of Good Teaching Award 2000, and Faculty Research Award 1997, Missouri University, College of Engineering. He is a Senior Member, Institute of Electrical and Electronics Engineers (IEEE), since 1998.

View full text