An efficient terminal and model order reduction algorithm☆
Introduction
Compact modeling of passive RLC interconnect circuits by model order reduction (MOR) techniques have been intensively studied in the past as a result of the urgent need to reduce the increasing circuit complexity. The most efficient and successful algorithms are based on Krylov subspace projection methods [3], [4], [5], [6], [7].
But existing MOR methods mainly focus on the reduction of the internal nodes. When there are many terminal nodes, the efficiency of the existing Krylov subspace methods will degrade significantly. There are several reasons for the low efficiency. First, the time complexity of the projection-based methods is proportional to the number of terminals of the circuits as moments excited by every terminal need to be computed and matrix-valued transfer functions are generated. Second, the poles of the reduced models are linearly increasing with the number of terminals, which make the reduced models much larger than necessary or even larger than the original models with dense matrices.
One way to mitigate this problem is by means of combined terminal reduction and MOR. Terminal or port reduction is to reduce the number of terminals/ports of given circuits under the assumption that some terminals are similar or correlated in terms of their timing information. Such similar or correlated terminals are justified by the facts that many terminals are indeed close to each other structurally during the mathematic approximation steps involved (finite element, finite difference, etc.). So their timing responses are similar also. Several terminal reduction algorithms have been proposed [8], [1], [9]. Recently, a terminal reduction method, called SVDMOR, has been proposed [8], [1], which is based on the low-rank approximation of input and output position matrices before the MOR process. The low-rank approximation can be carried out on the DC [8] or a specific order of moment [1]. However, our experimental results show that SVDMOR does not perform well when the numbers of the input and output terminals are quite different. The singular value decomposition (SVD) approximation is performed on the block moment matrix, which represents the response for both input and output terminals at the same time. So the approximation will not work well when the numbers of inputs and outputs are dramatically different. Basically the low-rank approximation or the number of independent terminals (or their correlation) may not be same for both input and output terminals. This typically happens when the numbers of input and output terminals are quite different. This is the case for many clock distribution networks and the signal nets in the memory circuits (word lines and bit lines) where you have a few driver (inputs) and many sinks (outputs).
Terminal reduction by SVD-based rank computation and terminal clustering via K-means method on terminal timing was proposed in [9]. The clustering is based on the higher order timing information. The method uses representative terminals to represent the reduced terminals. This method is very suitable for circuits with separate input and output terminals. But this method loses the timing difference between the representative terminals and their suppressed terminals.
In this paper, we propose a new SVD-based terminal reduction algorithm, called Extended SVDMOR or ESVDMOR method. Our approach is based on the SVDMOR method [1]. But the new method uses higher order moment information during the SVD approximation process to ensure that we can find the better correlations between input and output terminals. Also the ESVDMOR performs the SVD on input and output moment responses separately so that it can exploit the input and output correlations separately when they are different. We also show that by using the projection-based MOR method and the SVD-based terminal reduction framework, passivity requirements, which retain all the terminals as both input and output terminals, will not lead to effective terminal reduction. As a result, separation of the terminals into input and output is necessary for effective terminal reductions for SVDMOR-like methods. Experimental results show that ESVDMOR outperforms SVDMOR in terms of accuracy for the same size of the reduced models when the input and output terminals are quite different.
The paper is organized as follows. In Section 2, we review the SVDMOR method for model reduction with large number of terminals and show its weakness with experimental results. Section 3 presents our new ESVDMOR method. We first present main idea of the new terminal reduction method. Then we show how higher order moment information is represented for input and output terminal responses. After that we discuss some practical issues associated with the implementation, and present the whole terminal reduction and MOR flow of ESVDMOR. We also present a short discussion on the passivity issue in terminal reduction 4. The experimental results and conclusions are presented in Sections 5 and 6, respectively.
Section snippets
Review of the SVDMOR method
In this section, we briefly review the SVDMOR method for terminal reduction, which was proposed recently for reducing the terminals of interconnect circuits [8], [1].1
For a linear RLC interconnect network with input and output terminals, we can apply modified nodal analysis to formulate it
The new extended SVD-based (ESVDMOR) method
In this section, we present our new terminal and MOR algorithm, ESVDMOR. The basic idea of the new method is to perform the SVD low-rank approximation for the input and output terminals separately and use higher order moment information during the SVD approximation to find true terminal independency to ensure the accuracy of the reduced model.
Passivity discussions and terminal reduction effectiveness
For MOR, the input and output position matrices and are required to be the same for ensuring passivity in projection-based reduction framework. When and are not the same, passivity may not be ensured with existing projection methods. We notice that reduction by truncation balanced realization (TBR) can make passive reduction of RLCK circuits with different and [10]. But passive TBR is a very expensive process and does not scale to solve large problems.
One may think that one can
Experimental results
The proposed method has been implemented in MATLAB 7.0. We tested our algorithm on a number of real industry interconnect circuits from our industry partner. For all the examples, we apply both SVDMOR2 and ESVDMOR terminal reduction methods. The MOR operations are performed using PRIMA [6] for all the examples for both algorithms.
The first example, net27, has 14 inputs and 118 outputs with the model order of 182. Because there are more
Conclusions
In this paper, we have proposed a new combined terminal and model order reduction method, ESVDMOR, for compact modeling of interconnect circuits. The new method improves SVDMOR [1] by using higher order moment information for terminal responses during the terminal reduction and using separate SVD low-rank approximation on input and output terminals, respectively. The new method exploits the fact that input and output terminals may not have the same degree of correlations and it can better
Pu Liu (S’05) received his B.S. in Electrical Engineering from Inner Mongolia Polytechnic University, Inner Mongolia, China, in 1998, and M.S. degree in Control Theory & Engineering from Beijing Institute of Technology, Beijing, China, in 2002. He is currently a Ph.D. candidate in Electrical Engineering, University of California, Riverside.
His research interests focus on compact modeling and simulation techniques for VLSI circuits, architecture level thermal modeling and simulation. He has
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Pu Liu (S’05) received his B.S. in Electrical Engineering from Inner Mongolia Polytechnic University, Inner Mongolia, China, in 1998, and M.S. degree in Control Theory & Engineering from Beijing Institute of Technology, Beijing, China, in 2002. He is currently a Ph.D. candidate in Electrical Engineering, University of California, Riverside.
His research interests focus on compact modeling and simulation techniques for VLSI circuits, architecture level thermal modeling and simulation. He has published a number of papers in various conferences in electronic design automation field. He is an IEEE student member.
Sheldon X.-D. Tan (S’96-M’99-SM’06) received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999.
He is an Associate Professor in the Department of Electrical Engineering, University of California, Riverside. He was a faculty member in the Electrical Engineering Department of Fudan University from 1995 to 1996. He worked for Monterey Design Systems Inc. CA, from 1999 to 2001 and Altera Corporation CA, from 2001 to 2002. His research interests include several aspects of design automation for VLSI integrated circuits — modeling and simulation of analog/RF/mixed-signal VLSI circuits, high performance power and clock distribution network simulation and design, signal integrity, power modeling, thermal modeling, thermal optimization in VLSI physical and architecture levels and embedded system designs based on FPGA platforms.
Dr. Tan is the recipient of NSF CAREER Award in 2004. He also received the UC Regent's Faculty Fellowship in 2004, 2006. Dr. Tan received a Best Paper Award Nomination from 2005 IEEE/ACM Design Automation Conference, Best Paper Award from 1999 IEEE/ACM Design Automation Conference. He also co-authored book “Symbolic Analysis and Reduction of VLSI Circuits” by Springer/Kluwer 2005 and Advanced Model Order Reduction Techniques for VLSI Designs, by Cambridge University Press, 2007. He is an associate editor for Journal of VLSI Design and served as a technical program committee member for ASPDAC, BMAS,ASPDAC, ISQED,ICCAD.
Boyuan Yan received the B.Eng. degree in electrical engineering from Dalian University of Technology, China, in 2004, and the M.S. degree in electrical engineering from University of California, Riverside, in 2007. Currently, he is working toward the Ph.D. degree and his research interests are in the area of model order reduction of large-scale circuits and systems.
Bruce McGaughy received the B.S. degree in Electrical Engineering from the University of Illinois at Urbana/Champaign and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the University of California at Berkeley, in 1994, 1995 and 1997, respectively. He has conducted and published research in the fields of circuit simulation, device physics, reliability, electronic design automation, computer architecture and fault tolerant computing.
Prior to his current assignment, he worked for Integrated Device Technology (IDT), Siemens and Intel. In 1997, he joined Berkeley Technology Associates which eventually became Celestry and was acquired by Cadence in 2003. He has led the architecture and development of the hierarchical fast-SPICE simulator UltraSim since its inception at BTA in 1999. More recently he was group director for the circuit simulation R&D group at Cadence including Spectre, SpectreRF and UltraSim products from 2004-2005. Since 2005, Dr. McGaughy has been chief architect for Cadence simulation products.
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Some preliminary results of this paper were presented at IEEE International Workshop on Behavioral Modeling and Simulation (BMAS’06) [2], San Jose, CA. This work was sponsored by NSF CAREER Award CCF-0448534, NSF Grant OISE-0623038 and University of California MICRO Program (#04-088 and #05-111) via Cadence Design System Inc.