Elsevier

Integration

Volume 41, Issue 3, May 2008, Pages 413-425
Integration

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem

https://doi.org/10.1016/j.vlsi.2007.10.002Get rights and content

Abstract

Routing is one of the important steps in very/ultra large-scale integration (VLSI/ULSI) physical design. Rectilinear Steiner minimal tree (RSMT) construction is an essential part of routing. Macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase. Obstacle-avoiding RSMT (OARSMT) algorithms are useful for practical routing applications. However, OARSMT algorithms for multi-terminal net routing still cannot meet the requirements of practical applications. This paper focuses on the OARSMT problem and gives a solution to full-scale nets based on two algorithms, namely An-OARSMan and FORSTer. (1) Based on ant colony optimization (ACO), An-OARSMan can be used for common scale nets with less than 100 terminals in a circuit. An heuristic, greedy obstacle penalty distance (OP-distance), is used in the algorithm and performed on the track graph. (2) FORSTer is a three-step heuristic used for large-scale nets with more than 100 terminals in a circuit. In Step 1, it first partitions all terminals into some subsets in the presence of obstacles. In Step 2, it then connects terminals in each connected graph with one or more trees, respectively. In Step 3, it finally connects the forest consisting of trees constructed in Step 2 into a complete Steiner tree spanning all terminals while avoiding all obstacles. (3) These two graph-based algorithms have been implemented and tested on different kinds of cases. Experimental results show that An-OARSMan can handle both convex and concave polygon obstacles with short wire length. It achieves the optimal solution in the cases with no more than seven terminals. The experimental results also show that FORSTer has short running time, which is suitable for routing large-scale nets among obstacles, even for routing a net with one thousand terminals in the presence of 100 rectangular obstacles.

Introduction

Routing a net, finding a rectilinear Steiner minimal tree (RSMT) for a given terminal set, is one of the fundamental problems in very/ultra large-scale integration (VLSI/ULSI) physical design. Many algorithms have been proposed focusing on the RSMT problem. However, only a few RSMT algorithms take obstacles into consideration. In practical routing applications, macro cells, IP blocks, and pre-routed nets are often regarded as obstacles. Obstacle-avoiding RSMT (OARSMT) construction is often used as an estimation for wire length even delay throughout the process of routing. Therefore, we need efficient OARSMT algorithms in physical design. Garey and Johnson [1] proved that the RSMT problem is NP-complete. Thus, OARSMT problem is more complicated and polynomial-time algorithms can unlikely solve it exactly.

The OARSMT problem has been well studied for the case of two-terminal net. Lee et al. [2] presented maze algorithm to route two-terminal nets optimally. Some improvements on Lee's algorithm were proposed later [3], [4], [5], [6]. The line-probe routing algorithm was introduced in [7], [8]. This kind of algorithms is suitable for small-scale problems. Zheng et al. [9] proposed an algorithm, in which the searching space is restricted to a strong connection graph (implicit connection graph). The time and space complexity depend on the instance (the number of terminals and obstacle border segments). Wu et al. [10] introduced a sparse connection graph (track graph) to reduce the searching space efficiently and routed the shortest path based on the graph.

We need to route multi-terminal nets in the routing phase. However, routers often use the multi-terminal variant of the maze routing algorithm, which incurs the same space demand as that of the two-terminal variety and usually obtains solutions far from the optimal.

Ganley et al. [11] proposed an algorithm to construct the optimal three-terminal or four-terminal OARSMT. Then G3S, G4S, and B3S heuristics [11] were proposed for the cases with less than 20 terminals. Zachariasen et al. [12] gave an exact algorithm for finding an obstacle-avoiding Euclidean Steiner tree with less than 150 terminals. The O(mn) two-step heuristic [13] (m is the number of obstacles and n is the number of terminals) works well when the number of terminals is less than seven and obstacles are convex ones. There are some recent achievements [14], [15], [16]. Shi et al. [14] achieved short wire length but could only route the nets with less than 50 terminals, which could not meet the needs of routing full-scale nets. A rectilinear approach was proposed in [15], which has the limitation of handling blockages with complex shapes such as concave polygons and handling large-scale cases.

Thus, it still needs full-scale solutions to the OARSMT problem, which can handle more terminals in the present of convex and concave polygon obstacles with short length performance and high time efficiency. The major contribution of this paper is a full-scale solution based on two heuristics, namely An-OARSMan and FORSTer, to the obstacle-avoiding RSMT problem. A special data structure, track graph, is used in An-OARSMan. We present the T-reduction to delete redundant vertices and edges in the track graph. Then the searching space is reduced. An-OARSMan can obtain the optimal solution while the terminal number is less than seven and it is suitable for the common scale net routing with less than 100 terminals. FORSTer takes short running time. The full Steiner tree (FST) construction and detour method are used in the FORSTer algorithm, which makes it more practical for large-scale net routing with more than 100 terminals.

The rest of this paper is organized as follows. In Section 2, we introduce some basic definitions of the OARSMT problem, connection graphs, and the ant colony optimization (ACO). Section 3 proposes the An-OARSMan heuristic. In Section 4, the FORSTer algorithm is described in detail. Section 5 presents the experimental results and Section 6 concludes the paper. The partial of this work, i.e., the An-OARSMan heuristic, has been published in ASP-DAC 2005 [17]. This paper presents progress in large-scale extension and includes detailed analysis.

Section snippets

Basic definitions

Definition 1

The space under consideration is the plane with x- and y-coordinate axes and the L1-metric, i.e., the distance between two points (x1, y1) and (x2, y2) is defined as |x1x2|+|y1y2|. If all the edges of a polygon are either horizontal or vertical ones, then the polygon is called a rectilinear polygon. Here, we consider arbitrary rectilinear polygon obstacles without holes.

Definition 2

Considering polygon S as a set of points, a rectilinear polygon is x-convex if for any two points p1 and p2 in set S that

The An-OARSMan algorithm

For common scale net obstacle-avoiding routing, we introduce the An-OARSMan algorithm based on track graph here. An efficient method, T-reduction, is used to reduce the searching space.

The FORSTer algorithm

An-OARSMan works well for common scale nets. But to get a full-scale solution, we still need efficient method for large-scale nets. In this Section, we give a detailed description of the FORSTer algorithm for large-scale net obstacle-avoiding routing.

Experimental results

We have implemented these two algorithms in C language and performed it on a computer with Linux operating system. We first randomly generate the terminals by the usual random function. Then, we use the same random function to generate the boundaries of the obstacles. When an obstacle is constructed, we check if there are terminals inside it. If so, the obstacle is deleted. The obstacles are constructed to include all types of convex and concave rectilinear polygons, such as rectangle, L-shaped

Conclusions

Based on An-OARSMan and FORSTer, this paper introduces a full-scale solution to the rectilinear obstacle-avoiding Steiner minimal tree problem. With an efficient reduction method on the track graph, An-OARSMan keeps high wire length performance for common scale net obstacle-avoiding routing. The three-step heuristic, FORSTer, takes short running time for large-scale net obstacle-avoiding routing.

Acknowledgments

This work was supported in part by the Key Project of Chinese Ministry of Education under Grant no. 106008, the Specialized Research Fund for the Doctoral Program of Higher Education (SRFDP) of China under Grant no. 20050003099, and the National Natural Science Foundation of China (NSFC) under Grant nos. 90607001, 10531070 and 10771209.

Tom Tong Jing received the B.S. degree in electronic engineering and the M.S. and Ph.D. degrees in computer science from Northwestern Polytechnical University, Xi’an, China, in 1989, 1992 and 1999, respectively. He is currently a Research Associate at Electrical Engineering Department, University of California at Los Angeles. From September 1999 to April 2001, he was a Postdoctoral Researcher at Computer Science and Technology Department, Tsinghua University, Beijing, China. He was a Faculty

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    Tom Tong Jing received the B.S. degree in electronic engineering and the M.S. and Ph.D. degrees in computer science from Northwestern Polytechnical University, Xi’an, China, in 1989, 1992 and 1999, respectively. He is currently a Research Associate at Electrical Engineering Department, University of California at Los Angeles. From September 1999 to April 2001, he was a Postdoctoral Researcher at Computer Science and Technology Department, Tsinghua University, Beijing, China. He was a Faculty Member (Associate Professor from 2001 to 2004, Tenured Associate Professor from 2004 to 2006) at Computer Science and Technology Department, Tsinghua University. He was a Visiting Scholar at University of California at San Diego and Chinese University of Hong Kong. He has authored or coauthored more than 100 papers published in technical journals and conference proceedings. His research interests include electronic design automation (EDA), combinational optimization and algorithms, graph theory, and programming. Dr. Jing is a recipient of IEEE/ACM ASP-DAC Best Paper Award in 2005, ACM/IEEE ISQED Best Paper Nomination in 2005, and IEEE ASICON Outstanding Student Paper Award in 2003. He is a recipient of the Second Class Science and Technology Award by Ministry of Education of China in 2005. He is a recipient of the First Class Award for Excellence in Teaching by Beijing Municipal Education Commission in 2004 and the First Class Awards for Excellence in Teaching by Tsinghua University in 2002 and 2004, respectively. He has served as a TPC member of IEEE/ACM ASP-DAC 2006; the Secretary General, Chair of Physical Design and Interconnect Optimization TPC-Subcommittee, and Session Chair of IEEE/ACM ASP-DAC 2005; the Session Chair of IEEE ASAP 2005; a TPC member, a Panel Speaker, and Session Co-Chair of IEEE ICCCAS 2004; a Session Chair of ISCI 2004; the Secretary General and TPC member of IEEE ASICON 2003; and the Session Co-Chair of IEEE/ACM ASP-DAC 2003.

    Yu Hu received the B.S. degree and M.S. degree both in computer science from Tsinghua University, Beijing, China, in 2002 and 2005, respectively. Currently, he is a Ph.D. degree candidate in the Electrical Engineering Department at the University of California, Los Angeles. He worked with Xilinx Research Laboratory in the summer of 2006. He is currently a Graduate Student Researcher (GSR) with the Electrical Engineering Department at the University of California, Los Angeles. His current research interests include CAD for FPGA synthesis and ASIC physical synthesis. He is the author of over 20 technical papers in journals and international conferences, and the inventor of 4 patents in the field of CAD for VLSI designs. Mr. Hu received the outstanding graduate student award in 2005 from Tsinghua University. He has been a full member of Sigma Xi since 2007, and a student member of IEEE since 2004.

    Zhe Feng received the M.S. degree in computer science and technology from Tsinghua University, Beijing, China, in 2007. He is currently working towards the Ph.D. degree in the Department of Electrical Engineering, University of California, Los Angeles. His research interest focuses on synthesis and physical design for FPGAs, and physical design for ASICs.

    Xian-Long Hong received the B.S. degree from Tsinghua University, Beijing, China, in 1964. Since 1988, he has been a Professor in the Department of Computer Science and Technology, Tsinghua University, Beijing, China. He has published 5 books and more than 400 papers. His research interests include very large-scale integration (VLSI) layout algorithms and design automation systems. Prof. Hong has served as the steering member of Asia and South Pacific Design Automation Conference (ASPDAC) and the co-chair of technical program committee of. ASPDAC in 1999, 2004 and 2005 He has been an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I since 2002.

    Xiaodong Hu received his B.S. degree in applied mathematics from Tsinghua University, Beijing, China, in 1985, and his Ph.D. degree in operations research and cybernetics from Institute of Applied Mathematics, Chinese Academy of Sciences, in 1989. He was a post-doctor fellow at Rutgers Center for Operations Research, Rutgers University, in 1990–1991, a visiting associate professor at graduate school of information science, Japan Advanced Institute of Science and Technology, in 1993–1994, and a research fellow at Computer Science Department, City University of Hong Kong, in 1998–2000. Currently, he is a research professor at Institute of Applied Mathematics, Chinese Academy of Sciences. His research interests include combinatorial optimization and computer communication networks. He is the member of American Mathematical Society (since 1992) and member of IEEE Computer Society (since 1997).

    Guiying Yan received her B.S., M.S. and Ph.D. degrees in operational research from Shandong University, in 1989, 1992 and 1995, respectively. Currently, she is a Professor of Academy of Mathematics and Systems Science. From 1995 to 1997, she was a postdoctor fellow of Institute of applied mathematics, Chinese Academy of Sciences. She is now serving as an Editor of the IEEE Acta Mathematicae Applicatae Sinica.

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