Simulink^®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation

Abstract

As a solution for dealing with the design complexity of multiprocessor SoC architectures, we present a joint Simulink-SystemC design flow that enables mixed hardware/software refinement and simulation in the early design process. First, we introduce the Simulink combined algorithm/architecture model (CAAM) unifying the algorithm and the abstract target architecture. From the Simulink CAAM, a hardware architecture generator produces architecture models at three different abstract levels, enabling a trade-off between simulation time and accuracy. A multithread code generator produces memory-efficient multithreaded programs to be executed on the architecture models. To show the applicability of the proposed design flow, we present experimental results on two real video applications.

Introduction

Current embedded systems require flexible and high-performance architectures to concurrently perform multiple applications. An attractive architecture for these systems can be the use of heterogeneous multiprocessor SoC (MPSoC), which provide highly concurrent computation and flexible programmability [1]. Recent platforms such as CT3600™ [2] and Cell™ [3] are examples of heterogeneous multiprocessor architectures with 10–20 heterogeneous processors. A network router CRS-1 [4] based on an array of 192 configurable processor cores also illustrates this trend.

A typical multiprocessor architecture includes a set of CPU and memory subsystems (SS) interconnected via a communication network [5], as depicted in Fig. 1(c). The CPU subsystem includes one or more different kinds of processors (e.g. DSP for data-oriented operations, GPP for control-oriented operations or ASIP for application-specific computation), specific hardware components, and specific I/O communication as shown in Fig. 1(d). The heterogeneity of processors implies the need for multiple software stacks that may require different computation and communication performance. The software stack is organized in three layers as shown in Fig. 1(e): application software, hardware-dependent software (HdS), and the hardware abstraction layer (HAL) [6]. The application software may be a multithreaded application description, which makes use of high-level primitives (HdS API) to abstract the underlying platform. The HdS, which is made up of a thread library and specific I/O communication library, is responsible for providing application software with architecture-independent services (HdS API) such as thread scheduling and communication between different threads. The HAL is responsible for architecture-specific services (HAL API), such as context switching, interrupting service routines, specific hardware components, and specific I/O controls.¹

As the complexity of embedded applications and systems grows, the heterogeneous multiprocessor architecture integrates an increasing number of processors and hardware components. Designing and programming such complex multiprocessor architecture is now becoming a major challenge in the embedded system development. In conventional design approaches, hardware and software are usually considered separately and the hardware/software integration is done only at a late stage of the embedded system design process, when the hardware for the SoC is fully defined. The lack of early coordination between the design of hardware and software causes unacceptable delay and cost overheads. The most effective method for improving design efficiency is raising the level of abstraction to enable design space exploration and hardware/software codesign from the early stages of the SoC design process [7], [8].

SystemC [9] has become the preferred hardware–software codesign language, because it enables one to specify and simulate both software and hardware within a wide range of abstraction levels [10]. ROSES [11] and COSY [12] are examples of SystemC-based hardware/software codesign environments for SoC architecture. The design tools take a high-level SystemC model in which abstract modules embedding a set of functions communicate among themselves via abstract communication channels, and the tools gradually refine this set of functions to a detailed hardware and software architecture. However, these SystemC-based approaches have several limitations. First, a SystemC model is built manually after hardware–software partitioning. This manual build is error-prone and time-consuming, which limits the design space exploration. Second, SystemC is not a popular language for system designers to describe complex systems at an algorithm level of abstraction. Finally, a fixed sequence of functions calls for a module limits software code optimization such as buffer memory minimization. One needs to raise the abstraction level up to the algorithm level in order to overcome the above-mentioned limitations.

On the other side of the automation spectrum, Simulink [13] has been widely adopted as the prevailing environment for modeling and simulating complex systems at an algorithm level of abstraction. Designers can easily build algorithm models by assembling user or predefined functional blocks via a graphical user interface. Real-Time Workshop™ (RTW) and Simulink HDL Coder, tools provided by the environment, can automatically generate software and hardware from the algorithm model, respectively [13]. However, mapping and refining algorithm models onto complete MPSoCs are open issues in the Simulink community.

This paper presents an MPSoC design flow that enables systematic and automated MPSoC design from a high-level specification using the Simulink environment and SystemC language. More specifically, the proposed design flow allows a system designer to specify both a system at an algorithm level of abstraction and also a high level of mixed hardware–software system in Simulink, as shown in Fig. 1(a) and (b), respectively, and then automatically refine it to the targeted MPSoC hardware and software using SystemC, as shown in Fig. 1(c)–(e). In this way, one can have benefits from the use of Simulink during the higher-level modeling and SystemC during the lower levels.

For seamless hardware–software refinement, we first defined a Simulink combined algorithm/architecture model (CAAM) to specify abstract hardware and software architecture. This Simulink CAAM is the first level of mixed hardware–software model. From the Simulink CAAM, a hardware architecture generator produces architecture models at three different abstract levels: (1) virtual architecture for early development and validation of the multithreaded application software, (2) transaction-accurate model for fast verification of hardware architecture and OS library, and (3) virtual prototype for accurate system verification and performance estimation [6]. The design flow is followed by a multithread code generator that builds software stacks executable on the generated architecture models at different abstraction levels from the Simulink CAAM. The multithread code generator applies copy removal and buffer sharing techniques to produce memory efficient thread code [14].

The major contribution of this work is proposing an MPSoC design flow starting from an algorithm-level specification based on mixed hardware–software refinement. The secondary contribution is the memory optimization techniques applied during the multithread code generation and integrated into the proposed design flow. Although the current design flow does not support automatic parallelization techniques, different architectures and algorithm mappings can be manually evaluated at a fraction of the required time for manual work, since designers can easily capture high-level mixed hardware–software models from a Simulink algorithm model by using the graphical user interface and evaluating the generated target MPSoC at the implementation level in a short amount of time. This paper includes experimental results and analysis with a Motion-JPEG decoder and an H.264 video decoder as test cases to show the effectiveness of the proposed design flow.

The paper is organized as follows. Section 2 describes related work on MPSoC design flow. Section 3 explains the proposed design flow and the details of the mixed hardware–software abstraction levels. 4 Hardware architecture generator, 5 Multithread code generator describe the generation of hardware architecture model and multithread code generation, respectively. Section 6 summarizes our experimental results and analysis. Section 7 concludes and highlights directions for future work.