Dual-rail asynchronous logic multi-level implementation

Abstract

A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean network of complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes are designed based on DIMS, direct logic and NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection logic inputs is reduced significantly, since the number of nodes that should be supplied with the completion detection is less than in the case of the network structure that is based on simple gates. As a result, the improvement in sense of the total complexity and performance is obtained.

Introduction

Asynchronous logic attracts an increasing interest of designers because asynchronous (delay-insensitive—DI) circuits are extremely robust. This means, the design is able to adapt to variations of manufacturing process parameters, gate and wire delays, temperature changes, noise, etc. [1]. The correct function is guaranteed, only the operational speed changes adaptively. Furthermore, a DI paradigm is very similar to the synchronous one and generally, the DI design process follows the same steps as in synchronous logic design. As a result, the developed DI design flow can be easily incorporated into the design industry, since the tools and design processes are familiar to designers. The DI design process can be easier implemented, since a minimal delay analysis is required to ensure the circuit correct behavior. DI paradigm has additional advantages in designing complex circuits including substantially reduced crosstalk between analog and digital circuits, ease of multi-rate circuits cooperation and facilitation of component reuse [15].

The general disadvantages of DI asynchronous circuits with regard to the synchronous ones are high area and huge power consumption overheads, although the thermal distribution is uniform across the chip.

We propose a synthesis flow of multi-level DI dual-rail implementation. It is based on exploiting synchronous logic synthesis tools to produce a single-rail Boolean network of a two-level (AND-OR) nodes, and further transformation of the network into a dual-rail one. Based on results [18], each node is designed as a hazard-free structure. Finally, the technology-dependent mapping procedure is applied. For the comparison, several state-of-the-art methods are considered, where nodes are designed based on DIMS [13], direct logic [11], and NCL [15]. For the detailed comparison, the method [17], where each single-rail Boolean network node is designed as a simple gate (NAND, NOR, etc.) was chosen. We believe that this method is the closest one to our approach. Although [17] is supposed for designing some other class of circuits, it is clear that the method can easily be adapted for DI logic synthesis. Indeed, the Boolean network [17] is designed as a dual-rail hazard-free logic. The indication of the new input state and internal stability can be done using the completion detection (CD) logic proposed in this paper.

The main disadvantage of the method [17] is a large number of nodes that should be supplied with the CD—the completion detection must be provided for each simple gate. It is not the case of our approach, where the number of nodes of the synthesized Boolean network is significantly less than in [17]. Therefore, in our approach, the CD logic complexity is reduced, although the functional logic implementation complexity may be slightly increased (to ensure hazard-free implementation of the AND-OR nodes). As a result, the improvement in sense of the total complexity and performance is obtained. The other approaches to CD optimization can be found in literature. Namely, in [30], the optimization method based on evaluation of the gates relative timing was proposed. In [31], the method in a cost-aware manner was described.

The rest of the paper is organized as follows. In Section 2, the review of the related works is given. The information and notations regarding dual-rail logic is presented in Section 3. Also, details of DI logic behavior rules that are based on Seitz's strong and weak constraints [10] are described. Section 4 is devoted to the description of the model with modified weak constraints. Next, the node minimization constraint to ensure hazard-free implementation is formulated and the structure of the dual-rail network is proposed. Examples illustrating the state-of-the-art and our approaches are given. It is shown that our approach produces networks with significantly less number of signals the CD logic is supplied with. Section 5 describes the technology-independent and technology-dependent synthesis procedure. Experimental results are given in Section 6. Statements summarizing the results conclude the paper.