Elsevier

Integration

Volume 47, Issue 1, January 2014, Pages 123-129
Integration

Hardware implementation of tag-reader mutual authentication protocol for RFID systems

https://doi.org/10.1016/j.vlsi.2013.03.002Get rights and content

Highlights

  • Truncated multiplier is used to encode the password of RFID authentication protocol.

  • Protocol with truncated multipliers provides more security.

  • Better area and power saving of proposed RFID mutual authentication protocol is demonstrated.

  • An FPGA Implementation has done for proposed RFID mutual authentication protocol.

Abstract

Radio-frequency identification (RFID) is a recent technology that utilizes radio frequencies to track the object by transmitting a signal with a unique serial identity. Generally, the drawbacks of RFID technology are high cost and authentication systems between a reader and a tag become weak. In this paper, we proposed a protocol for RFID tag–reader mutual authentication scheme which is hardware efficient and consumes less dynamic power. Truncated multipliers are implemented in RFID tag–reader mutual authentication protocol system due to reduction in hardware cost and dynamic power. Experimental evaluation reveals that the proposed protocol with truncated multipliers provides more security than the earlier schemes. The proposed protocol is described in VHDL and simulated using Altera Quartus II. The functional block is implemented as hardware using an Altera DE2 Cyclone II (EP2C35F672C6) Field-Programmable Gate Array (FPGA).

Introduction

An RFID tag stores the information electronically which can be read from several meters away without having contact between tag and reader. Tag consists of an integrated circuit for handling data and an antenna for receiving and transmitting a radio-frequency signal. The RFID system utilizes one of three general band's low frequency (LF) at 125 kHz to 134 kHz, high frequency (HF) at 13.56 MHz, and Ultra HF at 860 MHz to 930 MHz [1], [2]. RFID tags contain a unique serial number namely electronic product code (EPC) that can individually identify every single tagged item [3], [4]. Electronic product Code Class 1 generation 2 (EPC C1G2) provides only very basic security tools using a 16 bits pseudorandom number generator (PRNG) [5]. The LFSR can be created using the Galois or Fibonacci configuration of gates and registers. Fibonacci implementation, the output from some of the registers is EX-ORed with each other and fed back to the input of the shift register. Fibonacci LFSR is more suitable for hardware implementation than the Galios LFSR [6], [7], [8]. A light authentication protocols that use only efficient bitwise operations (such as EX-OR, AND, OR, addition etc.) on tags have been defined in [9]. In [10] Hernandez-Castro et al. proposed an efficient protocol for low cost RFID tags in which number of addition operation reduced compared to [9]. An additional rotation operation is used for authentication protocol in [11]. Konidala et al. [12] proposed a protocol that utilized tag's access and kill passwords for the tag–reader mutual authentication scheme based on EX-OR operation.

In Peris-Lopez et al. [13] uses a MixBits function that require many iterations to complete, which leads to increase the hardware cost. Huang et al. [14] modified the Padgen function proposed by Konidala et al. and implemented a protocol in FPGA. Li et al. [15] proposed a EX-OR scheme for an efficient implementation of protocol. Schulte et al. [16] states that the power dissipation of a truncated multiplier is less compared to a standard multiplier. Wang et al. [17] states that truncated multiplier is used for lossy applications. Ko and Hsiao proposed an efficient array based truncated multiplier, which consume less power and utilized fewer hardware resources [18]. Selwyn discussed a various RFID Mutual authentication protocol in [19], [20] in order to identify the vulnerabilities in protocols. In another work Cho et al. [21] analyzed, securing against brute-force attack of a hash function based authentication protocols. All the above protocols are fails in any one of the following aspects such as cost, security, power consumption and possibility of backward processing of the operation or function. In this paper truncated multiplier is used to encode the information during a mutual authentication process, it reduces the hardware cost, strengthening security and consumes less power to perform this multiplication. In addition to that, number of bit processing is fewer which lead to reduction in the bit length and their no possibility of finding the information by performing backward processing. The rest of this paper is organized as follows. In Section 2, we present the background and its related work on the RFID reader-to-tag authentication protocol. The Proposed mutual authentication protocol is discussed in Section 3. Section 4 shows the simulation and implementation results of the mutual authentication scheme. Finally, we conclude the paper in Section 5.

Section snippets

Background and related works

RFID systems work, whenever a reader antenna emits a radio frequency signal. Tag pick up that radio signal and respond to a reader. Reader reads the signal which is responded by tag. The reader is act as a transceiver (i.e., a combination of transmitter and receiver) because their usual role is to request a tag and receive information from tag. The antenna can be a separate device, or it can be an integrated within a reader [1].

Proposed protocol

The protocol consists of three main component's tag, reader and server or database. In the proposed protocol, each tag has an individual EPC, Password (PWD) and a common architecture (truncated multiplier function) provided by manufacturer to encrypt PWD. The database has the information about EPC and PWD of all tags. It also has a common protocol architecture which is embedded in all tags.

Fig. 3. describes the proposed protocol communication step between a reader and a tag. The detailed

Simulation results

The proposed and other state of art RFID mutual authentication protocols are described using structural VHDL to produce gate level netlist and synthesized using Altera Quartus II tool. Here seven different RFID tag–reader authentication protocol namely LMAP, EMAP, SASI, Konidala Scheme, M3AP, Huang et al. and Lin et al. are considered for comparison [9], [10], [11], [12], [13], [14], [15].

The logical element requirement to perform a single time MixBits, Padgen, truncated multiplier function is

Conclusion

In this paper, an efficient RFID mutual authentication protocol is proposed whose functionality is verified using the VHSIC hardware description language. Truncated multiplier functions were examined for the tag–reader mutual authentication protocol in the RFID system environment. The proposed scheme is feasible in improving the weakness of the EPC global C1G2 communication authentication scheme. The hardware implementation of proposed RFID tag–reader mutual authentication protocol has been

V.R. Vijaykumar received his bachelor degree in Electronics and Communication Engineering in the year 1996 from Government College of Technology Vellore and subsequently he completed his M.E. degree in Communication Systems at Thiagarajar college of Engineering Madurai in the year 1997. He completed his Ph.D. in the area of Nonlinear Image Filtering from Anna University Chennai in the year 2008. He has 14 years of Teaching Experience. Currently he his working as Associate Professor in the

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    V.R. Vijaykumar received his bachelor degree in Electronics and Communication Engineering in the year 1996 from Government College of Technology Vellore and subsequently he completed his M.E. degree in Communication Systems at Thiagarajar college of Engineering Madurai in the year 1997. He completed his Ph.D. in the area of Nonlinear Image Filtering from Anna University Chennai in the year 2008. He has 14 years of Teaching Experience. Currently he his working as Associate Professor in the Department of Electronics and Communication Engineering, Anna University, Coimbatore, Tamil Nadu, India. His area of interest includes Image Processing, Signal Processing, Digital Communication and Low Power VLSI.

    S. Elango received the bachelor's degree in Electronics and Communication Engineering from Anna University Tamil Nadu, India, in 2010 and Master's degree in VLSI Design from Anna University, Tamil Nadu, India in 2012. At present he is working as Assistant Professor in the Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam, Erode, Tamil Nadu, India. His main research interests includes design of VLSI Data path elements, VLSI signal processing and Low power VLSI Designs.

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