Energy estimation in SystemC with Powersim
Introduction
The increase in functionality of Systems-on-Chip has favored the explosion in recent years of the market of small mobile and wireless devices. The constant progress in silicon technology led to a rise both in integration and clock frequency of electronics systems, increasing both power density and energy dissipation of systems. As a result, power dissipation has become an important constraint in the design of complex or portable systems [1]. The first necessary step towards low-power design is to estimate the power/energy dissipation of the system under development.
Power reduction requires a great amount of research and development to set up low power methodologies, low power design techniques and libraries and the associated CAD tools. New power reduction methodologies are needed and they must be supported by efficient tools. There is a need to optimize power in the overall system flow: system architecture, types of algorithms, hardware versus software trade-offs, design style and physical implementation. One particularly important domain is power analysis and optimization at system-level with seamless propagation of power constraints all over the design flow, down to device level.
System-level design is the key to fast SoC innovation with the capability to quickly try out different design alternatives, to confirm the best possible architecture, HW/SW partition and performance parameters, including power consumption, early in the design process. Recently, emphasis is moving towards power estimation at system level when some good ideas on optimizing power dissipation can drive the choice between different architectures.
Power analysis at system level is less accurate than at lower levels since the details of the real implementation of the functionality are not defined yet, but conversely the simulation time is much faster and the power saving opportunity with an optimization is much higher. In fact if power optimization at gate level is 15% more effective than fixing problems in test chips and power optimization at register-transfer level (RTL) can be 10 times more efficient than at gate level, at system level the power optimization opportunity can be one order of magnitude higher than at RTL [1].
SystemC is now a de facto standard for digital system design. It allows a fast simulation at different levels of abstraction enabling fast system level design, IP reuse, exchange of IP between different design teams and companies without giving the details of the hardware implementation. Some tools linked to the SystemC environment have been developed with the aim of adding power estimation in the SystemC description.
Section snippets
Related work
As said, power estimation can be performed at different levels of abstraction. A lot of work has been carried out in this field with a constant trade-off between accuracy and speed. Many tools and methodologies have been developed for power estimation at register-transfer level (RTL). For example, Coburn et al. [2] propose a paradigm to speedup power estimation at RTL. SimplePower [3] is an execution-driven, cycle-accurate, RTL power estimation tool. The framework evaluates the effect of high
The methodology
The aim of this section is to describe a methodology for the estimation of energy dissipation in a hardware described at any level of abstraction. In the following, we will define a measure space where the dissipated energy is the measure itself. Powersim was a direct consequence of the application of this methodology.
Powersim
Powersim is a C++ class library developed to be used inside a SystemC implementation. Its main purpose is the simulation of energy for the consumption of digital systems, by the direct application of the model described in the previous section.
Therefore its way of operation is based on monitoring the C++ operators, when called on SystemC data types. This allows the user to obtain the energy consumption of a functional block during a SystemC simulation without changes of the source code. The
Computational cost estimate of a JPEG encoder implementation
As a first example, we applied Powersim to a JPEG encoder RTL architecture. This encoder has been developed starting from a C++ program and then embedded in a SystemC wrapper. The high-level model has been then refined in more accurate models, until obtaining a clock cycle-accurate one. At last, the refined model has been translated in VHDL and implemented on an FPGA. The architecture implemented follows the “baseline” encoding process defined by the standard [22]. The baseline process simply
Power estimate of a microcontroller implementation
The first example does not involve Powersim energy models, since it was focused only on computational complexity estimation. In order to show the use of energy models, we tested Powersim with a real hardware, in particular with a DEMOJM board of Freescale Semiconductor Inc. This demo-board has MC9S08JM60 micro-controller on board with various other devices such as LEDs, buttons, buzzer, 3-axis accelerometer, and potentiometer. Furthermore the board allows, using an appropriate jumper, the
Conclusions
The Powersim software tool has been presented in this paper. The energy estimation performed by Powersim is simulative and derived from the application of a model based on the measure theory. It was tested to evaluate energy consumption and the computational cost of different architectures described in SystemC at behavioral level in a simple way, without changing the original code describing the architectures. Two examples are reported: a microcontroller firmware and a JPEG encoder. Energy
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