Elsevier

Integration

Volume 55, September 2016, Pages 194-201
Integration

Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

https://doi.org/10.1016/j.vlsi.2016.06.004Get rights and content

Abstract

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder.

Introduction

In recent years, battery powered mobile devices have been incredibly developed and almost every aspect of our lives has been affected by modern portable technologies. Therefore design of ultra-low power devices and circuits is extremely important nowadays.

Subthreshold circuit design is one of the most common methods for reducing power consumption, because minimum energy point (MEP) of a digital system, if available, is certainly located in subthreshold region [1]. But circuits in subthreshold region have more constraints and sensitivities in comparison with above threshold operation [2], [3]. One of the most determinative limitations is the performance which is affected by supply voltage and severely degraded in subthreshold region. Hence improving performance of subthreshold circuits is vital to meet market demand. For this purpose, several logic families have been introduced in [4], [5] and [6]. One of the most effective logic families is called Dual Mode Logic (DML) which can be switched between static and dynamic modes [7]. DML gates are implemented based on standard static CMOS logic with an additional mode select transistor, and therefore requires large number of transistors especially for creation of complex functions.

Gate Diffusion Input (GDI) logic is another low power logic family composed of just two transistors and is able to implement a wide range of dual input logic functions, with higher speed and less power consumption in comparison with standard CMOS or pass transistor logics [8]. In GDI logic output swing is reduced for some input combinations. Therefore additional buffer stage is required to solve this issue which in turn increases power consumption [9].

In this work, first we introduce transmission gate diffusion input logic (TGDI) as an enhanced version of GDI logic family, in which the reduction of output voltage swing has been fixed without additional buffer stage. In the next step we propose to use TGDI as a basis for a new dual mode logic family called “Dual Mode TGDI logic” or DMTGDI logic. Finally performance and power consumption of conventional DML, GDI and TGDI has been investigated and compared to DMTGDI logic for implementation of a single bit full adder block. Also post layout simulation is done to demonstrate negligible effect of parasitic elements on performance of this single bit full adder.

Section snippets

TGDI cell structure

Basic TGDI cell is created by replacing each transistor of GDI cell with a transmission gate. Fig. 1a and b demonstrates both GDI and basic TGDI dual input cells.

Since TGDI logic works based on complimentary inputs, it would be more convenient to have complimentary outputs as well. Fig. 1c shows TGDI cells with complimentary outputs. Boolean expression for TGDI logic is presented as follows [8]:out=G¯P+GNout¯=(G¯P+GN¯)=G¯P¯+GN¯

Transistor sizing of proposed logic is similar to an inverter in

Dual mode TGDI logic

By using dynamic logics, like domino, performance of digital circuits can be effectively enhanced, but high sensitivity of dynamic logics to process variations, makes them unsuitable for nanoscale technologies.

DML has been introduced recently as a logic family that can be switched between static and dynamic modes depending on applied clock input [7]. DML has higher performance and less power consumption in comparison with standard-static CMOS logic in dynamic and static mode respectively.

Simulation results and discussion

A single bit full adder which demonstrated in Fig. 7, has been implemented in conventional DML, GDI, TGDI and DMTGDI logics. These circuits have been used for simulation and comparison of performance, power consumption and effects of process variations on delay in these logic families.

Schematic of implemented full adder in DMTGDI logic is shown in Fig. 8. According to [7] optimal design in DML enhanced by connecting cascaded gates in type A and B alternatively. This methodology is also applied

Conclusion

In this paper, a new logic family called DMTGDI has been introduced based on two consecutive steps. First by replacing pass transistors on GDI logic with transmission gates in TGDI and then by modifying DML logic based on TGDI unit cell. Simulations results demonstrates that this logic family has superior performance and less energy consumption both in subthreshold and above subthreshold regions comparing to conventional DML and GDI logics, while inherits flexibility of DML and low energy

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