Full-V_DD and near-threshold performance of 8T FinFET SRAM cells

Highlights

• Full-V_DD and near-threshold operation of 8 T FinFET SRAM cell schemes are evaluated.

• Near-threshold operation is more attainable with 8 T rather than 6 T FinFET SRAMs.

• Reverse-biased inverter back gates reduce both leakage and power and increase SNM.

• Near-threshold 8 T FinFET cells can greatly reduce leakage and energy-delay product.

Abstract

We evaluate full-V_DD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM.

Introduction

For the past five decades CMOS scaling has offered improved performance from one technology node to the next. However, future bulk-CMOS scaling faces considerable challenges due to material and process technology limits [1]. Obstacles to the increased scaling of bulk CMOS include short-channel effects, sub-threshold leakage, gate-dielectric leakage, and device-to-device variations [1]. Currently two of the main challenges are the considerable increase of standby power dissipation and the increasing variability in device characteristics which in turn affects circuit and system reliability. The aforementioned challenges will become more prominent as CMOS scaling approaches atomic and quantum-mechanical physics boundaries [2]. There are continuing efforts to extend silicon scaling through innovations in materials and device structure.

One of these innovations are FinFET transistors. Double-gate FinFETs are able to continue CMOS scaling by overcoming these scaling obstacles [3]. One of the most important features of FinFETs is that the front and back gates may be made independent and biased to control the current and the device threshold voltage [4]. This ability to control threshold voltage variations offers a means to manage the challenge of standby power dissipation. FinFET is considered a promising technology that can impact the immediate future due to its high-performance, low leakage power, reduced susceptibility to process variations, and ease of manufacture using current processes [1]. These features make FinFETs a strong candidate to bridge the technology gap between mainstream bulk CMOS and non-Silicon devices.

FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage power makes FinFETs a promising option for memories, which are widely used in most digital systems. Leakage power is very important in memories. Memory access requires only one or very few memory rows at a given time; the great majority of memory cells draw only leakage power. In microprocessors, the clock network power consumption due to memory devices (i.e., cache memory, register, and pipeline registers) accounts for 51% of the total power [5]. Applying FinFET technology to memories can save significant power. A drawback of FinFET technology is that it requires more area overhead than bulk-CMOS [6]; this is due to required spacing between fins as well as interconnect spacing if independent front and back gates are used. There has been research in which the area of proposed FinFET static random access memory (SRAM) cells is compared with bulk-CMOS SRAM cells [7]. Cache modeling tools, such as CACTI-FinFET [8] and FinCACTI [9], [10], have also been developed to predict power, delay, and area values for FinFET-based SRAM cache memories. While higher area overhead can be a disadvantage for memory types that boast high density, such as dynamic random access memory (DRAM), the low leakage current and high speed offered by FinFETs are a great advantage for SRAMs, which are often used in digital systems due to their higher read and write speeds.

In this paper we focus on using FinFET technology to improve SRAM speed, operating energy, and leakage current. Table 1 [6], [11], [12] compares the leakage and on-current, or drive current, of FinFET and bulk-CMOS at two similar technology nodes, 25 nm and 10–14 nm, used by other researchers. The data from this table supports the claim that FinFETs manage leakage current better than bulk-CMOS transistors. Better suppression of leakage current lowers the power of SRAMs and also enables FinFET SRAMs to have larger read static noise margins than their bulk-CMOS counterparts [3]. However, FinFET SRAMs can exhibit data stability issues due to their quantized sizing [13]; this is because non-integer fin counts are not physically possible. In addition, the on-current of FinFETs is also larger than bulk-CMOS transistors; this results in FinFETs operating at higher speeds and lowers the delay of SRAM read and write operations. Other studies have also demonstrated that FinFET SRAMs have higher performance than bulk-CMOS SRAMs [14].

In this paper we examine the application of FinFET technology to eight-transistor SRAM cells. In Section 2 we discuss background information on SRAM subsystems and back-gate biasing strategies for FinFETs. 8T FinFET SRAM cell design options are presented in Section 3 and the simulation models and setup is presented in Section 4. In Section 5 we present the simulation performance results of 8T FinFET SRAM schemes for full-V_DD operation. Section 6 presents near-threshold performance for the 8T FinFET SRAMs. In Section 7 we present the FinFET SRAM performance for alternate array configurations for both full-V_DD and near-threshold operation. Performance under parameter, voltage, and temperature variations are presented in 8 Performance under parameter variations, 9 Performance under voltage variations, 10 Performance under temperature variations, respectively, for both full-V_DD and near-threshold operation. Lastly, we provide a few concluding remarks in Section 11.