Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC
Introduction
Three-dimensional integration is a critical technology as it delivers a high throughput with minimum power requirements. Through-silicon vias (TSVs) based on three-dimensional integrated circuits (3D ICs) generate one of the best implementations due to their unique interconnected structure. The interconnected path of TSVs can be extremely short given that the vertical dimension goes directly through the vias in silicon. The use of TSVs to access memory is a promising solution for memory wall issues.
TSVs are usually closely bundled together as a cluster [1], as illustrated in Fig. 1. Given the increasing demands for TSVs in one limited planar area, crosstalk issues between adjacent TSVs have become more serious. The capacitive crosstalk of one p+ doped substrate significantly depends upon the input signal patterns. The signal quality in one cluster may be affected by the opposite flips of neighboring TSVs. This variance can be much larger than that of one conventional 2D IC, where the victim signals are only affected by a limited number of aggressive signals.
Crosstalk issues in a TSV-based 3D IC have caught the attention of both academic and industrial experts. However, most work has focused on the theoretical analysis of crosstalk models [2], [3], [4], [5], [6], [7], [8], [9]. Some researchers have proposed several TSV crosstalk suppression schemes based on manufacturing process adjustments [10], [11], in addition to guard-ring TSVs [12], [13], [14] and coaxial TSVs [15], [16]. However, these optimization schemes may increase production cost or further impair the already low TSV yields. In recent years, researchers have focused on non-process-challenge solutions to suppress crosstalk. Kumar R et al. applied conventional 2D codec schemes to a 3D VLSI IC [17]. However, this system encounters challenges, specifically its high overhead, which may interfere with its application in the 3D IC. Various crosstalk suppression scheme layouts have also been proposed such as ShieldUS [18]. ShieldUS relays TSV clusters during runtime by employing the most inactive TSVs as shield TSVs and placing these around active TSVs to reduce signal patterns with serious crosstalk [18]. However, overhead is still a significant challenge. For example, it requires one large crossbar to map each TSV signal, which may be very costly.
The present study proposes a new optimization scheme, namely the dynamic data split, to relieve crosstalk issues in TSV clusters with little overhead or redundant TSVs. A TSV delay model based on the presented simulation program with integrated circuit emphasis (SPICE) model is first introduced, after which the numerical results of the presented investigation on the delays of victim TSVs are provided, specifically when these are affected by different neighboring signal patterns. The proposed scheme is then described in detail. The proposed study intends to leverage the large variance in the delay time of a victim signal at different aggressive signals and to achieve the overall gains by trading low crosstalk level switching patterns with high crosstalk level switching patterns. The presented scheme is also compared with other schemes, such as static or dynamic data mapping, to generate comprehensive evaluations based on bandwidth improvements, cost, and generalities.
Section snippets
TSV noise coupling model
A coupled TSV can be modeled as a twin-wire model, wherein the insulation layer lies between the metal and substrate, thereby creating a metal-insulator-semiconductor (MIS) structure. The equivalent SPICE model presented in this paper is illustrated in Fig. 2 [19].
The TSV capacitance, CTSV, is given by Eq. (1). Parameters hTSV, rTSV, and tOX represent the TSV height, TSV radius, and insulation thickness, respectively. Parameter εox is the dielectric parameter of the TSV capacitance, which is SiO
Crosstalk classification of TSV clusters
The signal integrity of each TSV in one M×N array was affected by the adjacent 8 TSVs for one 3×3 TSV cluster, as presented in Fig. 4. All of the aggressive TSVs (TSVij) are in blue, where (i,j)∈{(x,y)|0≤x<3, 0≤y<3, and xy≠1}, whereas the red TSV in the middle is the victim, TSV1,1. The crosstalk level of any M×N TSV cluster was determined by the worst case of the cluster. Although the victim TSV was affected by diagonally presented aggressive TSVs, the coupling capacitance of the diagonally
Other static and dynamic mapping schemes
The mapping schemes aims to use stable TSVs as guard TSVs and place them around active TSVs to eliminate crosstalk, as presented in Fig. 8. Mapping schemes generally include static mapping and dynamic mapping.
The static mapping scheme requires previous knowledge in terms of signal stability. Those signals (usually the upper part, i.e., MSBs) can be used as shields for the lower part (i.e., LSBs) [21]. However, previous knowledge is not generally available.
The dynamic mapping scheme does not
Evaluations
The presented evaluation is based on three characteristics: bandwidth improvement, generality, and hardware cost. We used a trace-driven simulator to study both the address accesses and instruction fetch requests to the L2 cache and used real-world benchmarks, such as the SPEC2006Int, SPEC2000Fp, and SPEC2000Int.
Conclusion
The present study focused on the improvement of the transmission bandwidth in one TSV-based high speed system by eliminating noise coupling issues. We proposed a novel scheme called the dynamic data split and compared it with other mapping approaches. We first discussed a delay model based on the TSV SPICE model and used the knowledge gained from it for further quantitative evaluation. We then implemented the proposed dynamic data split scheme together with other mapping schemes for comparison
Acknowledgments
This work is supported in part by the National Natural Science Foundation of China (61176037). We would also like to thank the Department of Microelectronics and Nanoscience at Shanghai Jiao Tong University.
Qin Wang received her B.S. degree from University of Electronics Science and Technology of China, Chengdu, China in 1997, received M.S. from Nanjing University of Aeronautics and Astronautics, China in 2000 and Ph.D. from Shanghai Jiao Tong University in 2004. She has been an associate professor at the Department of Microelectronics and Nanoscience, Shanghai Jiao Tong University. Her research interests include 3D IC, high speed on-chip interconnect and deep learning.
References (23)
- et al.
Delay-efficient bus encoding techniques
Microprocess Microsyst.
(2009) - S. Pasricha, Exploring serial vertical interconnects for 3D ICs, in: Proceedings of the ACM/IEEE Design Automation...
- et al.
Fast and accurate analytical modeling of through-silicon-via capacitive coupling
IEEE Trans. Compon. Packag. Manuf. Technol.
(2011) - et al.
Electrical modeling and characterization of through Silicon Via for three-dimensional ICs
IEEE Trans. Electron Devices
(2010) - T. Song, et al., Analysis of TSV-to-TSV coupling with high-impedance termination in 3d ICs, in: Proceeding of the 12th...
- C. Liu, et al., Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC, in: Proceedings of the ACM/EDAC/IEEE...
Accurate formulas for the capacitance of taperes-through Silicon Vias in 3D ICs
IEEE Microw. Wirel. Compon. Lett.
(2014)Electrical modeling and characterization of shield differential Through-Silicon Vias
IEEE Trans. Electron Devices
(2015)- et al.
Reliable 3D clock-tree synthesis considering nonlinear capacitive TSV model with electrical-thermal-mechanical coupling
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD)
(2013) - et al.
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Trans. Des. Autom. Electron. Syst. (TODAES)
(2009)
Effectiveness of p+ layer in mitigating substrate noise induced by Through-Silicon Via for microwave applications
IEEE Microw. Wirel. Compon. Lett.
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Qin Wang received her B.S. degree from University of Electronics Science and Technology of China, Chengdu, China in 1997, received M.S. from Nanjing University of Aeronautics and Astronautics, China in 2000 and Ph.D. from Shanghai Jiao Tong University in 2004. She has been an associate professor at the Department of Microelectronics and Nanoscience, Shanghai Jiao Tong University. Her research interests include 3D IC, high speed on-chip interconnect and deep learning.
Zhenyang Chen received B.S degree in Micro Electronics from Shanghai Jiao Tong University, Shanghai, China in 2012, and received M.S degree in Engineering of Integrated Circuits from Shanghai Jiao Tong University, Shanghai, China in 2015. He currently works as a software engineer in the Software Service Group of Intel Asia-Pacific R&D Center, Shanghai, China. His research interest includes high-speed interconnection technology and noise analysis on TSV-based 3D VLSI integrated circuits.
Jianfei Jiang received his B.S. degree in Electrical Engineering from Zhejiang University, Zhejiang, China, in 2000 and M.S. degree in circuits and systems from Shanghai Jiao Tong University in 2007. He is an assistant professor at the Department of Microelectronics and Nanoscience, Shanghai Jiao Tong University. His research interests include high speed on-chip interconnect, low power circuit design and high speed circuit design.
Zheng Guo received his B.S degree in Electronic Engineering from Shanghai Jiao Tong University, Shanghai, China in 2002, received M.S. degree in Communication and Information System from Shanghai Jiao Tong University, Shanghai, China in 2005, and received Ph.D. in Computer Science from Shanghai Jiao Tong University, Shanghai, China in 2016. He is now an engineer in Shanghai Jiao Tong University. His research interests include side channel attack and IC design.
Zhigang MAO received his B.S degree in Electronics Engineer from Tsinghua University, Beijing, China in 1986 and Ph.D. in Information & Signal Processing from RENNES university, French in 1992. He has been a professor in Department of Electronics technology of Harbin Institute of Technology before 2006, and now is a professor in the Department of Microelectronics and Nanoscience, Shanghai Jiao Tong University. His research interests include high performance logic circuit design, low power circuit design, security and fault tolerance of hardware.